Sagar Soni

Analog Design Intern @ Microchip Technology | Nit Rourkela | SCL Mohali | IIT Jammu | Shri Mata Vaishno Devi University

Sheopur, Madhya Pradesh, India

About

Experience

  • Analog Design Intern at Microchip Technology Inc.
    Jan 2026 - Present · 6 mos

  • Project Trainee at SEMI-Conductor Laboratory
    Jan 2024 - May 2024 · 5 mos

    Study of failure mechanisms in 180nm CMOS processes

  • Research Intern at Indian Institute of Technology Jammu
    May 2023 - Jul 2023 · 3 mos

    SRAM based In-memory Computing in VLSI Domain.

  • Summer Intern at Shri Mata Vaishno Devi University
    Jul 2022 - Aug 2022 · 2 mos

    Open Source Internet of Things Platforms