Austin, Texas, United States
Design verification engineer with 7+ years of industry experience verifying complex blocks in GPU memory and texture subsystem. Experienced in creating test plans, building scalable and portable UVM testbenches, coverage, SystemVerilog Assertions, Perl scripting. Major accomplishments include verifying ray tracing engine, building memory subsystem cluster bench, leading L2 cache and ACE converter blocks verification, developing base credit-debit, register UVCs and clock-enable driver, monitor to be extended and reused across subsystems. Graduated with Master's in Computer Engineering from North Carolina State Univeristy. Coursework included Advanced CPU architecture, GPGPU Architecture, Digital ASIC Design, ASIC Verification and Verification of Memory Controller for 3D DRAM (an independent study under Dr. Paul Franzon). Developed simulators for trace processor, nine stage OOO superscalar processor and analyzed their performance across different benchmarks. Created the verification model for memory controller scheduler block for 3D DRAM memory controller. Developed golden reference models for verification of pipelined LC3 micro-controller for my verification coursework project. Programming Languages: Verilog, SystemVerilog, SystemVerilog Assertions (SVA),C, C++, UVM, Perl Tools : Synopsys VCS, Synopsys Verdi, Cadence IES, Git, Perforce, Eclipse DVT Concepts : Ray Tracing, Cache Coherency, Traslation & Page Tables, ACE, ACE-Lite, Static Timing Analysis (STA), Object Oriented Programming (OOP).
Ray Tracing Engine • Developed UVM testbench from scratch to verify box, primitive and instance transforms. • Generated floating point stimulus by hierarchical constraints, command line randomization. • Created tests with all box, primitive, matrix flavors (hit/miss/watertight/infinity/NaN). • Completed unit verification of features OBB, IIN ahead of schedule for top-level bringup. • Added trace replay support to read vector file and create sequence items for driver.
Memory Subsystem Cluster bench • Integrated 10+ unit benches (caches, translations units, compression engines, cache rinse blocks, ACE converter, Synopsys AXI VIP) to create memory subsystem cluster bench. • Added scripts to update non-portable unit bench code to compile, run clean in cluster bench. • Generated page table mappings and loaded into Synopsis VIP to service page walk requests. • Created read, write, atomics, compressed, invalidation and shoot down sequences. • Developed cluster level UVM RAL model and UVM agents to service multiple daisy chains. • Worked with Graphics Core Top to integrate cluster bench into their environment. L2 Cache • Led a team of three with responsibility of GL2C cluster, quadrant, compression bench. • Developed cache preloader to initialize data/tag/LRU rams with vectors or random data. • Added wrapper classes and DPI calls to integrate Samsung AMD Joint Compression codec. • Successfully verified features (writeback crawler, out-of-order metadata cache) for tapeout. • Created script to convert GL2 benches from AMD DJ flow to Samsung Sim flow. YUV Compression Wrapper • Critical block added as a late feature for a project; Quickly developed scoreboard for bringup. • Created transaction class to store metadata, compressed data requests, states for a GL2 request. • Added scoreboard support for GL2 requests merging, metadata caching, per state timeouts. Translation Cache • Updated translation cache testbench for 128B Page Table Entries (PTE), cacheline prefetch. Methodology • Created base credit-debit, register bus UVCs to be extended and reused across subsystems. • Instantiated base clock-enable driver, monitor objects in base UVCs for clock gating. • Added pure virtual methods in base UVCs to extend and add interface specific functionalities. • Developed generic memory preloader to backdoor preload any behavioral memory models.
• Individual ownership of module (GL2ACEM) between GL2 cache and System Coherent Interconnect; Support for GL2 cache transactions, Register Programming, ACE-Lite Protocol verification, Middle of Test Reset verification . • Methodology team member - Develop and implement ideas for scalable, portable benches to reuse across projects. • L1C verification team member - Checker for coherency and cache data; Stimulus for reads, scalar and vector atomics. • Ownership of module (L2AGT) between clients and GL2 cache; Verified translation and routing algorithm. • Created an address generator by analyzing address requirements and address-sharing constraints across units. • Developed a framework to generate virtual and physical addresses, access permissions to be preloaded into TLBs. • Analyzed ARM Memory Management Unit (MMU-500) and methods to integrate it into GPU memory sub-system. • Debug daily regression failures in unit/top level and verify that bug fixes conform to the specification. • Created best practices to make the test bench scalable and portable for reuse across multiple projects. • Worked with the PPA team to create stress stimulus and check design for any performance issues. • Conduct Unreachability (UNR) analysis using formal to identify dead code in design; Used testplans and functional coverage for L1C, L2AGT, GL2ACEM to make them tapeout ready. • Collaborate with the RTL, Arch teams to identify potential deadlock issues and brainstorm to find a feasible solution.
• Commissioned systems for different industries including :- - - tube mill systems for customers in India (Nezone tubes, Inframat Alloys) and abroad (Al-Yamamah Steels, Jeddah). - - drive panels for mill, calendar applications and pneumatic panels for curing presses in MRF plants at Pondicherry, Medak, Arakonam and Trichy. - - gear box test rigs in Hindustan Aeronautics Limited (HAL), Bangalore and Ashok Leyland, Chennai. - - Parker’s first renewable energy project in India – 1 MW solar power plant in Hyderabad and also tested Battery Energy Storage Systems (BESS). • Solid understanding about different communication protocols including PROFIBUS, PROFINET, CANopen, DeviceNet, MODBUS and Ethernet. • Provided system solutions for applications in printing, packaging and paper industries. • Handled post-commissioning service calls for program optimization.
• Trained in basics of Parker Hannifin verticals namely Hydraulics, Filtration, Seals, Fluid connectors, Instrumentation, Automation. • Got acquainted with the processes involved in these verticals by visiting factory locations in Mumbai (Hydraulics, Instrumentation), Bangalore (Filtration), Nagpur (Fluid Connectors), Hyderabad (Fluid Connectors) and Chennai (Automation, Filtration, Seals). • Assisted in lean strategy implementation and ISO documentation of warehouse in Mumbai. • ‘Know Your Neighbor’ program – Mapped the potential vendors and customers for Parker in and around Chennai. • Got introduced to industrial automation by assisting in erection and commissioning of a slitter lineup in Jindal Aluminium, Bangalore.