Taipei, Taipei City, Taiwan
Senior hardware professional with 14+ years of experience in SoC validation and high-speed I/O. Currently serving as a Tech Lead directing an 8-person team supporting the Google gChip division. Expert in translating complex Micro-architectural Analysis and HPC data into actionable quantitative evidence for architectural optimization and power-performance (PnP) refinement.
▪Micro-architectural Analysis: Lead a team of 8+ engineers in leveraging Hardware Performance Counters (HPC) and Perfetto to identify bottlenecks; provided critical analysis for cluster configuration transitions (e.g., 1P+4E+2LL to 1P+4E+3LL), resulting in a 7% CPU power YoY improvement for the gChip division. ▪Data-Driven Optimization: Supervise the correlation of power-rail metrics with HPC data to visualize IP efficiency (CPU/GPU/NPU) during complex 3rd-party flagship benchmarking, providing gChip architects with actionable insights. ▪Meta Strategic Collaboration & ODM Management: Direct a dedicated sub-team as the core technical interface for Meta Wearable projects (e.g., XU4); managing ODM partners to ensure 100% completion of validation test items and providing technical solutions to secure on-time EVT→DVT transitions.
▪Customer Technical Enablement & Design-in: Served as the primary technical interface for Samsung and LG, driving Thunderbolt 3/4 integration from initial architectural schematic/layout reviews through high-volume manufacturing (HVM). ▪PHY/SI Optimization & Certification: Provided expert hardware tuning and Signal Integrity (SI) solutions to resolve complex PHY bottlenecks, securing 100% "first-time-right" Intel TBT Logo certification for flagship series such as LG gram and Samsung Galaxy Book. ▪Validation Automation & Global Collaboration: Architected automated test frameworks and coordinated with R&D teams in Israel/USA to resolve Power Delivery (PD) and firmware issues, reducing customer debugging cycles by 20% and accelerating time-to-market.
▪System-Level Validation Management: Directed electrical validation for high-density server systems, overseeing resource allocation and project milestones to ensure on-time delivery for tier-1 clients. ▪Technical Mentorship & Process Standardization: Developed standardized validation protocols and training modules, accelerating junior engineer onboarding by 50% and increasing departmental efficiency by 20%.
▪ Making All Operations manual for signal measurement. ▪ I / O interface USB, HDMI, PCIE3, DDR3, SATA, Ethernet, and DisplayPort to verify if they violate Specification ▪ Optimize the test flow to increase test efficiency by 50%
▪ Establish the hardware that verifies the motherboard. ▪ I / O interface USB, HDMI, PCIE, DDR3, SATA, Ethernet, and DisplayPort to verify if they violate Specification ▪ Compose reports for measurement data. ▪ Familiar with Tektronix high-frequency oscilloscope.