Yokohama, Kanagawa, Japan
Skilled and experienced LSI Digital Engineer with 13+ years of experience in RTL design, verification, and backend implementation, specializing in high-speed, low-power IC design using advanced node processes (5nm, 7nm, 12nm, 16nm, 28nm). Proficient in Cadence Innovus, Synopsys PrimeTime, and various scripting languages.