Rohit Patel

About

Experience

• Etched (Full-time · 1 yr 9 mos)
  • SOC lead
    Jun 2026 - Present · 2 mos

  • MTS -SOC design
    Nov 2024 - Present · 1 yr 9 mos

    Building chips for super intelligence!

• Sr Staff SOC design Engineer at Infineon Technologies
  Apr 2022 - Nov 2024 · 2 yrs 8 mos

• Staff SOC design at Cypress Semiconductor Corporation
  Jun 2019 - Apr 2022 · 2 yrs 11 mos

• Asic/SoC Design at Intel Corporation
  May 2016 - Jun 2019 · 3 yrs 2 mos

• Member of Technical Staff at Sibridge Technologies
  Jul 2013 - Jun 2016 · 3 yrs

  Lead Team of Engineers to deliver silicon proven IPs and IP based system solutions. Major responsibilities are, - Specification and feasibility study of IP - IP architecture definition and Review - Lead the team of engineers to develop the IP from specifications to pre-silicon validated IP. - Interact with client to understand the requirements to provide the IP solutions. - Interact with Verification team to monitor over all IP verification activity. Major IP portfolio worked on, - Ethernet IP portfolio includes, - UNH certified 10/100/1000 Mbps Ethernet solution which includes 10/100/1000 Mbps MAC with GMII/SGMII/RGMII/TBI Interface with 10/100/1000 Mbps PCS. Also supports AVB, EEE, PTPv2 feature support. - 10 Gbps MAC solution with XGMII/XAUI Interface support and PCS. SATA portfolio : - SATA gen2/gen3 Host and Device IP solutions. - SATA gen3 AHCI (Advanced Host Controller Interface) solution.