San Francisco, California, United States
13+ years of experience in Computer Systems Engineering. Passionate about quality and performance at the boundary of software and hardware. Fueled by curiosity and the next big challenge. Homelabber turned threat hunter. Enjoying the newfound (to me) intersections of automation and threat intel, observability, network engineering, and cloud. Certified: 2026 - CompTIA Security+ 2023 - Design for Six Sigma (DFSS) Green Belt
Zero Escapes for performance regressions! Authored and Testing and Reporting automation flows protecting yearly $170B+ annual revenue across 6.2M vehicles. Developed tools in Python and Jenkins to address growing needs to keep platform performance at the center of our products. Built relationships with platform feature developers across teams to teach them how to get meaningful feedback from the platform and analyze their performance data relating to their feature's impact to overall system performance. Worked to ensure safety compliance and reliability, via thorough performance testing of in-vehicle embedded systems with common Android and Unix-based profiling tools. Maintained a robust testing and data collection pipeline, with reporting capability to track performance regressions between Hourly builds, allowing for faster bisecting of the offending changeset. Reported out Key Performance Indicators (KPIs) on a per-line and per-hardware-setup basis for enhanced visibility for PMs and Directors.
Improved feature set of NVMe controller simulation platform to enable rapid development of firmware in parallel with ASIC during early stages of hardware development. Understood the needs of FW team, and worked closely with ASIC and architecture teams to develop a robust hardware abstraction layer (HAL) to allow the same code to target multiple platforms. Built and unit tested behavioral models of components of the controller. Upon readiness of ASIC and FPGA platforms, leveraged cross-platform system level tests and debugging to root cause bug sightings as firmware or simulation issues, making it easier to develop future products. Responsible for debugging and memory profiling in a multi-threaded, scheduled, Linux application environment, and occasionally FPGA debugging.
Supported design customers and drove enhancements for RTL integration tool used by 1000+ engineers. Developed tool for visualization and debug of complex design collateral which achieved a departmental recognition. Exploited features of UNIX environment to identify and reduce design tool flow performance bottlenecks. Shared and promoted best known methods and debug practices, improving customer productivity. Increased reliability of compute services by detecting and reporting spurious failures (false negatives).
Created VR experiences with cross-platform software and spatial audio technology. Developed multimedia capture and creation workflows using C++ and MATLAB. Built audio plugins and learned multi-threaded application best practices. Presented technical demos to potential clients at local conferences.
Assisted in the testing of performance monitor behavior. Wrote test cases to validated performance monitor behavior on PCIE interconnect and DDR subsystem. Learned basic DDR4 signaling architecture to write test cases. Became comfortable manually tracing signal paths across many Verilog design files, some of which were many tens of thousands of lines long.
Wrote Perl scripts in UNIX environment, automating simulation and data mining tasks related to electrical reliability of functional blocks of server CPU design layout. Assisted register file layout designers by locating areas of potential improvement by Excel dashboards of simulation electrical violations. Programmatically relaxed design constraints of over-constrained signal paths. Filtered signal paths based on device connections using proprietary schematic and netlisting tools.
Wrote automation scripts in UNIX environment for many internal customers. Debugged existing automation and tool flows. Wrote and debugged Perl and Tcl. Implemented, deployed and managed automated nightly regression testing of design tools. Ensured tool release quality via pass/fail and tool quality comparison tests. Maintained tool metrics generation and metrics comparison dashboard scripts. Taught others how to use system upon leaving internship.