Istanbul, Türkiye
PROJECT MANAGEMENT : • Member of PMI (Project Management Institute), 2014-2015 • Project Management Professional Training, 2014, 2019 • Member of "Change Management Program" of Ericsson, 2012 KNOWLEDGE : • VHDL, Verilog, SystemVerilog, UVM • Architecture of Xilinx FPGAs • Architecture of Altera FPGAs • Architecture of ARM Cortex M3 and ARM9, Xilinx MicroBlaze soft processor • Xilinx ISE, EDK (SDK,XPS), Chipscope • Altera Quartus • Synplify, Modelsim, NCSim • Synopsys Design Compiler, PrimeTime • Atrenta Spyglass • Matlab, Simulink • Tcl, Perl • C, Pascal, Assembly, Visual Basic • Signal Processing • Data Communication (802.11, I2C, PCIe, SDIO, UART, Bluetooth, SDH ) • Cryptology COURSES : • DO-254 Design Assurance Guidance Airborne Electronic Hardware Training from Aldec (3 days) • Emdedded Development Kit, SDK, XPS, Microblaze system development (5 days) • TCL scripting (2 days) • PERL scripting (2 days) • ARM Cortex-M3 SoC Design (3 days) • ARM7/9 SoC Design (3 days) • Atrenta Spyglass (Design rools check tool for ASIC) (2 days) • Introduction to WLAN (2 days) • Synopsys Design Compiler (RTL synthesis tool for ASIC) (3 days) • Synopsys PrimeTime (STA-static timing analysis tool for ASIC) (3 days) • Advance Synplify Premier • Time Management • Remote Team Effectiveness • Team Building with 5 Competences • Digital Design Best Practices • Synplify Pro and Synplify Premier • MATLAB / Using Matlab (2 days) • MATLAB / Simulink (2 days) • Embedded System Development with Xilinx Embedded Development Kit (5 days) • Fundamentals of Xilinx FPGAs and VHDL (5 days) • Advanced designing with FPGAs (5 days)
Chief Technology Officer (CTO)
- FPGA Project Management and Team Lead - SDIO 4.0 IP Generation Project Management - SDIO 4.0 IP Generation Verification Lead - SDIO 4.0 IP Generation FPGA Implementation
Digital hardware design of WLAN 802.11 a/b/g/n modem. FPGA implementation, verification, validation.
Digital hardware design of cyrptology systems for military purposes and FPGA implementation
Digital design of an STM-16 SDH multiplexer, FPGA implementation and validation