Courtice, Ontario, Canada
Senior Test Engineer with 15+ years of experience in hardware verification, post-silicon validation and automation development. Results-driven leader with strong technical skills, hands-on knowledge and experience mentoring junior team members. Proven record of driving innovation and influencing positive change. Organized, dependable and adaptable with excellent communication skills and a strategic approach to problem-solving.
* Diagnostics Release Lead for AMD’s leading Data Center Instinct AI accelerators Mi300A/X and latest RDNA 4 gaming GPU. * Responsible for on-time delivery of diagnostic suites to critical AMD teams including PEO, Board Ops, CE over life of product (ASIC bring-up to production ramp/sustaining). Involved building diag packages, writing release owned test code, testing/regression, debugging issues, releasing package. * Created comprehensive plans/timelines for release activities including board allocations, resource planning, test tracker/release metrics tools, SW tool readiness, code branching, Jira ticket creation, weekly release meetings. * Lead role for driving innovation and team initiatives to standardize release process, automate testing and deployment of diags, develop tools to log metrics, implement new features in diag suites and reduce test time. * Collaborated with various cross-functional teams to resolve issues blocking production, improve yields, debug CI failures, assist RMA teams with reproducing fails, resolve diag dependency issues with upstream teams. * Led introduction of CDL based diags to GPU diag team for Mi300A program. Created initial CDL Build/Test implementation in Diag Release Automation system which became template for future APU/CPU programs. * Led development of next generation Diag Execution Wrapper and WPKG build/packaging tool to support new test framework with greatly reduced overhead resulting in significant test time savings. * Senior member of team. Provided leadership and mentoring to students, delivered training on release process and new solutions, provided planning and oversight of tasks to junior team members for established programs. * Experience with pre-silicon emulation, GIT source code version control, Gerrit/GitHub code review and collaboration tools, SW Continuous Integration, Jira issue and project tracking tool, system setup, OS installation * Awards: Test Time Reduction, Diagnostic Execution Wrapper/WPKG Tool
* Responsible for automation development and infrastructure enablement for supported teams. * Worked with several validation teams to assess their state of automation, identify and prioritize potential projects based on ROI and make recommendations / budgetary asks to management. * Developed an automated system for HDMI Protocol Compliance Testing using an Agilent Capture/Analyzer Tool and remote control of target system reducing the time required for this task from 4 days to 1/2 day. * Developed an automated solution for HDMI Signal Integrity measurements using Agilent and Tektronix oscilloscopes (Tek/Ag VISA) in C++, Ruby and Python resulting in 60 percent man-hour savings for this task. * Led enablement effort for AMD's first Client/Embedded ARM program. Defined methodology for Android OS deployment in validation labs, investigated Android automation techniques, recommended lab/network infrastructure, drove Android OS requirements with SW tools and test framework teams. * Coordinated the extension of AMD Internal Validation network to ASIC/Platform labs allowing these teams to benefit from AMD common test execution framework and network based PXE OS/Driver installs.
* Responsible for validation of assigned ASIC blocks (ACPI/PM, Timers, HD Audio, Hyper Transport) including test plan development, electrical measurements, protocol/feature verification, unit/integration and functional level testing, triaging issues found during validation. (SB700/SB800/SB900) * Worked with other post silicon validation teams to identify test coverage gaps and redundancies. Analyzed ASIC bugs and test escapes from previous validation cycles to improve test coverage and shorten validation time. * Defined requirements for new SW tools and diagnostics targeting low coverage areas. Worked with SW teams to dry-run new tools in validation environment. * Interfaced with board design teams to drive validation requirements into test platforms to ensure testability of silicon features. Worked with ASIC designers to drive DFT features into silicon to improve ASIC testability. * Developed the first Marginal Silicon Validation plan for SB products and drove its execution for SB800/SB900 resulting in the discovery of several silicon issues (SATA, USB) in time for the next silicon spin. * Co-led an initiative to introduce comprehensive protocol testing for USB and SATA interfaces using 3rd party device emulation tools resulting in accelerated silicon bring up and improved protocol level test coverage. * Automation Lead: Drove automation strategy and initiatives for the group. Led the development of several large automation projects including: * A rack-based system for automated testing of test platforms driven by NI Teststand/Labview. * Automated USB and SATA Hot-Plug test solutions to eliminate need for operators to manually perform tasks. * Display Test Automation system prototype to capture / compare still images replacing human operators watching video monitors for display corruption.
* Measured signal integrity issues in 400/800MHz DDR2 Memory Tester to extend its performance and improve correlation to Motherboard test. * Investigated drive strength and ground bounce of FPGAs, high-speed clock drivers for next gen tester design. * Created production test plans and quality control guidelines for memory tester boards.
* Developed and supported production ATE memory test solutions for largest customers. * Responsible for all aspects of projects including review of customer requirements, DUT board HW design, test code development, verification and debug, release to production, production support. * Interfaced with customers to co-develop test solutions, determine root cause of field failures and improve quality by driving corrective actions back to DRAM suppliers. * Monitored production yields and performed Failure Analysis. Worked with Quality Engineers and manufacturing teams to identify and resolve issues. * Developed a 2-pass technique for testing higher speed DDR memory on existing testers extending the life of production test equipment by several years. (Technical Achievement Award) * Developed software to interface ATE testers to data collection systems and robotic auto-handlers. * Designed in-line solution to program SEEPROM devices during memory test eliminating process step and need for stand-alone programmers. * Familiar with ISO 9001, QMS documents, Quality Management. (6-Sigma, Lean Mfg., TQM) * Strategic Team Lead: Developed test strategy and wrote memory test specs. Prepared business cases/RFQs. Evaluated next gen testers, made purchase recommendations. Taught workshops, mentored junior employees. * SRED Representative: Identified projects and wrote submissions for Scientific Research and Experimental Development (SRED) tax credit. (Largest site submission ~ $100k savings) * Awards: Technical Achievement Award: DDR Test Development, Merit Awards: IBM Test Support, SRED Tax Credits