Melbourne, Victoria, Australia
Electronics Engineer with a Master of Engineering (Electronics) from RMIT University and 3 years of industry experience at Siemens EDA (formerly Mentor Graphics). At Siemens EDA, I worked on the Veloce emulation platform, contributing to clock generation design, real-time implementation, and advanced debug features using C/C++ and Verilog. My work focused on optimizing performance and strengthening hardware–software integration within complex verification systems. At RMIT, I expanded my expertise in FPGA design and real-time systems, developing HDL-based digital architectures and simulation workflows. My Master’s project involved building a Machine Learning–enhanced FPGA receiver system for V2X communication in automated vehicles. I hold a Bachelor’s in Electronics & Communication Engineering (Top 10%, multiple merit scholarships) from Thapar Institute of Engineering & Technology. Core interests: VLSI Design | FPGA & RTL Design | Embedded Systems | EDA Technologies | AI and Machine Learning Technical skills: C++, Verilog, SystemVerilog, Python, MATLAB, Questa, Quartus, Xilinx ISE
As a part of the team, I worked on numerous projects in the Emulation Division. Primarily, the focus was on Hardware-Software Codesign. My projects included Offline Waveform Capture And Debug, Clock Generation and Real-time Peripheral Connections with Veloce Emulators. During my time at the company, I honed my skills in C/C++ coding as well as HDL coding. My continuous use of Veloce Strato and Veloce X hardware as well as Questa for waveform debugging made me proficient in the use of the company's emulation and simulation products. My work also introduced me to communication tools like JIRA and confluence.