New Taipei City, New Taipei City, Taiwan
10+ years of experienced Verilog and System Verilog design skill in USB 2, USB 3.1 and USB4. Architect and designer of USB4 IP design and interface, including Logical Layer, Transport Layer, and Configuration Layer. Enable FPGA emulation of all USB specifications and lead to improve RTL for FPGA timing and compatibility. Fully engagement of system validation, compliance certification, and customer support tasks of USB2/3 hub. Familiar with 8051/Arm programming and experienced co-development with FW programmers. Possess a master degree in EE.