Saratoga, California, United States
Dr. Ranko Šćepanović is an executive leader with more than 30 years of experience spanning advanced silicon, AI infrastructure platforms, ASIC technologies, and hardware/software co-design. He has held senior leadership roles across startups, mid-size companies, and large-scale organizations — including Vice President and Fellow at LSI Logic, CTO & SVP Engineering at eASIC, and VP Engineering at Intel. Throughout his career, Ranko has specialized in bridging architecture vision, scalable silicon execution, and system-level productization. He has led the development of complex chip platforms, breakthrough technologies, infrastructure-class silicon systems, and differentiated IP across networking, cloud, wireless, defense, and AI-related applications. Renowned for consistently achieving right-first-time silicon across generations and process nodes, Ranko has built and led high-performance global engineering organizations across the U.S., Europe, India, and Malaysia. His leadership contributed significantly to eASIC’s growth, public S-1 filing, and eventual acquisition by Intel. More recently, Ranko has focused on next-generation AI infrastructure architectures, scalable accelerator integration, and system-level platform strategies for power- and compute-constrained AI environments. With 130+ issued patents spanning algorithms, EDA, architectures, security, and IC/systems technologies, he is recognized for combining deep technical insight with disciplined execution and strategic platform thinking.