Bengaluru, Karnataka, India
SUMMARY OF SKILLS • Over 11 years of engineering experience that covers multiple aspects of ASIC/SoC/IP Verification. Expertise at handling multiple projects, multiple protocols, and working with clients in different time zones at a time within a single organization. Mentoring entry-level engineers and helping organizations to grow in terms of improving the quality of verification solutions delivered to the market. • In-depth knowledge of entire chip design process including IP/SoC Verification Flow, Micro-architecture features, PCIe Express (Gen 1 to Gen 5), CXL 1.1 IP and SoC Verification, IA32 architecture CPU Verification and Validation. Developing complete UVM testbench from scratch after understanding the design specifications, Expertise at developing Test Plan and Function Coverage Plan looking at the design specification. Proficient at Functional Coverage and Code Coverage analysis and providing feedback to the verification team. Expertise at root causing regression failures to Test Issues, Environment Issues, and RTL bugs in shorter duration. • Extensive hands-on experience in RTL design verification using System-Verilog and UVM Methodology. • In-depth knowledge of IA32 Architecture, PCIe Express Protocol(PCIe Gen 1 to PCIe Gen 4). Having a basic understanding of PCIe Gen 5 and CXL 1.1 protocols. Complete knowledge related to PCIe protocol enhancements targeted towards server domain(PCIe SR-IOV, PCIe MR-IOV, and PCIe NVMe). Ramping up on solutions like USB over PCIe. • Significantly contributed to Industry-standard protocol development forums. – PCIe Express(PCI SIG Member) • Collaborative team player with strong technical, communication, and problem-solving skill. TECHNICAL PROFICIENCIES: • Programming/Scripting Languages: Verilog, System Verilog, C, C++, TCL, Perl. • VIP(Verification IP Development): PCIe Gen 3 TL Layer VIP module owner, PCIe SR_IOV VIP solution architect and developer, PCIe Physical Layer 8b/10b encoder/decoder VIP architect and developer, PCIe Gen 3 Physical Layer LTSSM(FSM) module development architect and developer(LTSSM Specific Verification), Resolving VIP bugs filed by customers in shorter duration, Helping customers to verify the initial version of RTL with hotfixes. • Protocols: IA32 CPU Architecture, PCIe Gen1 to Gen5, CXL 1.1, PCIe NVMe, PCIe SR_IOV, PCIe MR_IOV • Methodology: UVM, • Tools: Synopsys VCS, ModelSim, Verdi, DVE, Verdi, Design Compiler, FPGA debugger, Protocol Analyzer, Logic Analyzers, debugger, and Oscilloscopes, Mentor Tools, Cadence NCsim, Cadence vManager, Cadence Xillium Simulator.
I am part of performance verification team to measure performance for NBIO and CPU performance..
Working with Intel PCIe Client: 1) Verification of PCIe Gen 1/2/3 architecture. 2) Working on Code Coverage and Functional Coverage of PCIe TL Layer Modules. 3) Leading the team of 5 people to achieve success in project. 4) Working on PCIe features like PTM, IOSF, LTR, OCQ and All_Supported. 5) Working on a PCIe protocol debug. Working with Intel PCH SOC team: 1) Working on DTS/TT block for verification. 2) Debugging the test cases for SOC.
I am working in Alten Calsoft as Senior Verification Engineer. I am working in Qualcomm as Client. 1) Working in Video SS group to verify latest video architecture. 2) Working closely with designers to close the testplan of video group. 3) Working on an integration of new blocks in debug modules.
Client: Samsung India Research Private Limited.. 1) Working on developing the PCIe SOC plan. Integrating the PCIe VIP on platform. 2) Working on developing the MMU SOC plan. Integrating the MMU VIP on platform. 3) Working on a Samsung security block for SOC. Developing subsystem and SOC level testplan. 4) Working on integrating of I2C, UART, SPI and QSPI VIPs. 5) Working on Samsung security block subsystem and SOC level verification. 6) Working with client directly to gather the requirements.
Focusing on verification of upcoming CPU's targeted towards SOC's, Desktop,Laptops and Gaming Consoles. Mainly using UVM methodology,assembly and C++ env. 1) Work on latest AMD processor debug with directed and random test cases. 2) Work on performance analysis between two families of processors. 3) Work on developing the testplan and testcases. 4) Working with designers to layout test plan for new features. Developing test cases and running regressions. 5) Working with SOC team to debug issues found in overall design. 6) Total focus on a x86 architecture debug and verification.