Cupertino, California, United States
I am a pro-active RTL Design and Verification Engineer with a keen eye on playing the Power, Performance and Area trade-offs in Design and effectively debugging critical design errors with my verification skills. My philosophy " If things stopped being easy you are on the right path"
• Developed a reusable coverage block (with cross and transition coverage) for the tensor compute block’s new State buffer memory interfaces. • Built and deployed a novel verification flows for incremental coverage aggregation, enabling faster merges (85% less time to merge) improving total regression run time and overall quality of verification.
• Contributed to Tegra SoC memory controller subsystem – chip-to-chip hub verification. • Developed scoreboard checks to ensure correctness and protect test intent in performance testcases. • Created Perl automation scripts (using cursor) for coverage and constraints generation for CHI (coherent hub interface) AMBA Protocol interface. • Gained hands-on experience with UVM methodology, SystemVerilog, and Synopsys VCS/Verdi.
• Contributed to the development of a 22nm low power wireless IoT chip, with a primary focus on developing and managing SystemVerilog (SV) and Universal Verification Methodology (UVM) based test cases. These responsibilities extended to both the top-level design and subsystems, with a particular emphasis on integrating the EUSART module at the top level. • Engaged in a project involving a 40nm chip with a focus on Time Division Multiplexing (TDM), I2S module. Acquired expertise in the testbench components at the module level, formulated a comprehensive test plan, and crafted directed test cases to identify RTL bugs in newly integrated features. Produced coverage reports at the module level, specifically for the TDM component. • protocols: AMBA APB, AHB, and AXI and MMLDMA • Worked on testbench (stimulus, agent, monitor, checker) development and verification of having c-based reference model inside the testbench.
• Working on the QSPI model. Verified QSPI using directed testcases for various QSPI modes. • Integrated QSPI memory models from different vendors into the UVM based verification testbench. • Ported testbenches and testcases from VCS environment to Questa and helped in finding transition errors. • Developed regression files in Silicon Labs Design Environment. • Checked for firmware generation issues and worked with in the team to run the testcases successfully in Silicon Labs design flow. • Developed an architectural understanding and designed to tape-out lifecycle of Wireless SOCs