San Francisco Bay Area
Experienced ASIC development leader with a strong vision for methodology, architecture, design and validation. Proven track record of structured milestone driven execution, attracting/retaining top talent, and building a motivated team based on mutual trust. Enable culture of excellence with focus on consistent/quality execution
Handle vendor handshake for external IP (PCIe, HBM, Ethernet, CPU, low power peripherals); customize, verify and integrate into world's first inference ASIC: Sohu
Working on first generation AI inference engine called Sohu. In charge of bringing structure of execution to the broader verification team. Handling vendors, IP's, external teams to bringup HBM based memory subsystem in the chip
##As a Team Leader## - Leading a talented team of managers and individual contributors to help define, design and verify subsystems in Cisco’s chiplet based silicon for AI customers (prior gen: https://www.cisco.com/c/en/us/solutions/collateral/silicon-one/silicon-one-p100-processor-ds.html) - Architectural contributions focused on simplifying complex flows, optimizing area/power - Coordinate deliverables with remote IP teams - Led an ever-evolving design/verification strategy/methodology, focusing on productivity, automation, adopting cutting edge techniques and technology - Collaboration with vendors on tool evaluations/adoptions, VIP integration and licensing/pricing models - Keen eye for hiring and retaining right talent ##As an Individual## - Block, superblock, chip-level, post silicon validation efforts with impeccable record of quality & consistency - Expertise in SystemVerilog (UVM), Verilog, Verdi, VCS, VC Formal, Spyglass, C/C++, Constrained randomization, Coverage closure, Gatesims, Performance/Architecture modeling, PTPX, Memory compilers, Memory controllers, HBM3/3e, PHY, DRAM, AI/ML scripting & automation (Python/Perl) - Architected reusable verification/design/PD components - Static and dynamic power projections using both vectorless and vector based PTPX runs
Responsibilities include - Implementing, testing, debugging and software profiling of device drivers using on-chip debugging tools - Power and Performance tweaking for dual core based embedded platforms
Responsibilities include - Software based modeling and analysis of futuristic memory power management schemes - Developing test beds, for characterization of power consumption in laptop and server platforms