Bengaluru, Karnataka, India
As a DFT Engineer, my comprehensive skill set spans across key aspects of Design For Testability (DFT) and Digital Design. I have honed expertise in Scan Insertion, Scan Compression (EDT), ATPG Pattern Generation, Coverage Analysis, On-Chip Clock Controller, Scan Pattern Simulation, JTAG, Boundary Scan, and MBIST Insertion. In Digital Design, I've handled projects involving Combinational and Sequential Circuit Design and have a solid understanding of the basics of Verilog HDL. When it comes to software skills, I'm adept in the automation language TCL, and am comfortable working on both Linux and Windows Operating Systems. My HDL proficiency includes Verilog, and I regularly use the GVIM text editor. I am well-versed in various EDA Packages including Tessent (Scan, TestKompress, MBIST), ModelSim, and Design Compilers. Furthermore, being fully immersed in the DFT domain, I am actively seeking opportunities that allow me to leverage my well-rounded expertise. I am always ready to embrace challenges that come my way, as I firmly believe in continuous learning and growth. If you have a role in the DFT domain that can benefit from my skill set, please feel free to connect with me.