Vernier, Geneva, Switzerland
Electronics Engineer with 12+ years of experience designing and delivering high-performance first-time-right ASICs for CERN’s particle accelerator complex. My work spans from concept to mass manufacturing, bridging digital design, verification, testing, and volume production. At CERN, I led the digital implementation of the world’s first wafer-scale stitched pixel sensor, a 26×1.9 cm² radiation-hard ASIC for the ALICE Inner Tracker upgrade, called MOSAIX. I’ve also managed large-scale production testing campaigns for the transceiver lpGBT and GBTX chips (over 500 000 units tested) and led the design and QA environment for complex chip submissions involving international collaboration across seven institutes. My technical background includes digital-on-top ASIC flows, RTL to GDS flow with radiation-hard techniques, FPGA design, power integrity analysis and is complemented by leadership experience mentoring young engineers and managing industrial partners. Beyond design, I’ve built frameworks to harmonize EDA tools and design kits across institutes, enabling the broader high-energy physics community to access advanced CMOS technologies. This experience taught me how to merge technical excellence with organizational coordination. I’m passionate about innovation, collaboration, and delivering first-time-right silicon in challenging environments. Currently seeking opportunities in ASIC design, digital implementation, or technical leadership roles where I can continue to drive reliability and creativity in chip development.
I have been involved in several projects over the past years. Projects and roles: • Digital design lead of the MOSS/MOSAIX ASIC, a 26cm wafer scale stitched monolithic sensor with 8x 10.24 Gb/s transmitters • Development of volume production testing of the lpGBT ASIC (500k units) • Design of the digital core of BLMASIC in 130 nm, a radiation hard 1 mA ~ 1 pA current probe • Physical verification and tapeout of ABCSTAR radiation hardened ASIC in 130 nm • Development of a 2.56 Gb/s Eye-Opening-Monitor in 65nm • Development of a Built-in-self-test for PLL to estimate jitter at production stage • Development of the lpGBT radiation hardened ASIC in 65nm, a transceiver upto 10.24 Gb/s • Development of a CDR/PLL radiation hardened ASIC in 130nm • Development of a test environment and the volume production for the GBTX radiation hard ASIC, a 4.8 Gb/s transceiver Some of the skills developed: • Digital-on-top IC design • Verification methodologies • RTL-to-GDS flow • Power integrity analysis / EMIR analysis • Schematic/Layout entry • Post-layout simulations • Radiation-hard by design • Radiation effects • FPGA design, PCB design • Testbench development • IC Volume testing, QA/QC • EDA tools, Programming • FPGA firmware development • Verilog, VHDL • IC volume production • Problem solving, reports, meetings, team work • Multi-cultural and dynamic environment
Developed skills in debugging, testing and troubleshooting. Problem solving, reports, meetings, team work in a multi-cultural and dynamic environment • Embedded systems using GPIB, JAVA programming, scripting (MATLAB, octave, python) to acquire data from instruments and confirm the ASIC performance and behavioural model • Developed skills in debugging, testing and troubleshooting; know-how of measuring instruments, such as oscilloscope (jitter and data analysis), network analysers, logic analysers, frequency-meters and a flavour of optoelectronics 1. FPGA firmware Design - VHDL coding - Testbench development - Altera, Xilinx 2. Laboratorial characterizaiotn of ASICs - Development complex laboratories systems for chip characterisation: phase-noise measurements, CDR/PLL/DLL characterisation - Use of python/GPIB for instrument control 3. Radiation qualification of ASICs - Heavy-Ion testing at the Cyclotron, Louvain-la-neuve - X-ray at CERN - Proton testing at CERN - Two Photon Laser testing (pulscan) 4. IC Volume production, QA/QC - Test system commissioning at the industrial partner - IC handler (Multi-Test 9510) intregration with custom hardware - Software development for the test suite - +80k units
Electronics class Electrónica Geral
"In order to save battery life and to reduce chip heating, many analog circuits are equipped with power-down features, which means the circuit will be in idle when is not used. During this state, the internal nodes voltage level is determined by the subthreshold voltage characteristics of the devices, current leakage and by the applied external signals. Depending on these node voltages, short-circuit paths and asymmetrical stress conditions can occur. In order to detect these situations, it is necessary to use analysis that rely on structure recognition, and on the voltage propagation algorithm" My work consisted in the implementation of algorithms in C++ and in visual interfaces in CADENCE/SKILL. These were developed in order to visually aid the user where short circuits or possible shot-circuits could occur during the power-down mode of the circuit. For more information follow http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6339384&isnumber=6339379
Electronics class Electrónica (for Biomedical and Physics students)
Electronics class Teoria de Circuitos Electricos; The paper entitled "Robust Optimization-Based High Frequency Gm-C Filter Design", published in DoCEIS 2011, was developed under this scope