Bengaluru, Karnataka, India
AI-SoC verification engineer specializing in system-level HW/SW co-validation of processor and complex subsystem architectures. I operate across microarchitecture and software boundaries, ensuring architectural correctness, memory hierarchy integrity, and performance-critical behavior in pre-silicon environments. My work spans microarchitectural verification of processor subsystems — including pipeline control, privilege transitions, exception handling, and memory ordering — along with integration and validation of heterogeneous SoC components. I have driven bring-up and architectural validation of embedded compute cores, AI/ML acceleration engines, and critical infrastructure subsystems such as shared cache hierarchies, high-throughput data movement engines, address translation units, and secure interconnect controllers. I design scalable UVM-based verification environments and leverage C/C++-driven validation flows to stress corner cases, expose cross-domain integration issues, and ensure system-level stability under realistic workloads. I am particularly interested in heterogeneous compute platforms, AI accelerators, and energy-efficient architectures — focusing on how hardware abstractions and microarchitectural design evolve to support modern AI and data-intensive workloads.
🚀 Founder & Lead Architect @ NARI – Next-Generation Architecture Research Institute (Weekend Venture) "Pioneering Tomorrow’s Hardware, One Clock Cycle at a Time" 💻 Mission: By weekday, I’m a SoC/CPU Architect (Design Verification); by weekend, I lead NARI—a passion-driven initiative to democratize hardware innovation. We’re advancing processors, AI accelerators, and energy-efficient computing through open-source tools, education, and reproducible research. 🔧 What We Do at NARI: ✅ Education: Teach RISC-V design/verification with SystemVerilog/UVM, Scala/Chisel, and gem5 for microarchitectural exploration with hands-on lab. AI/ML hardware accelerators (GPUs, TPUs, NPUs) and performance tuning (Gprof, VTune, ChampSim). ✅ Open-Source Innovation: Build end-to-end silicon workflows with open-source tools, Jupyter Notebooks, and GitHub Codespaces. ✅ Research: Design next-gen CPU cores, memory systems, and domain-specific architectures (XPUs). 🌟 Why I’m Here: Mentor engineers, students, and hardware rebels preparing for the semiconductor revolution. Collaborate on open-source silicon projects, workshops, or cutting-edge research. Partner for guest lectures, EDA toolchains, or custom courses. 🌱 Join the Movement: NARI isn’t just an institute—it’s a global community reshaping computing. Whether you’re: Exploring modern advanced computer architectures, Simulating RISC-V/ARM/x86 systems in gem5, Optimizing AI accelerators for energy efficiency… Let’s design, verify, and build the future—together. 📩 DM to Connect & Learn More about the courses/services we offer: #RISC_V #CPUDesign #OpenSourceHardware #AIAccelerators #ChipDesign #ComputerArchitecture #Semiconductor #VLSI #HardwareVerification #Gem5 ☕ Powered by coffee, code, and a love for transistors.
Membership no.-287385 Member of society of Artificial intelligence/Computer Science/Electrical engineering/Scientific computing
Working on the pre-silicon verification and bring-up of a TrustZone-enabled smart wearable SoC based on Arm secure and non-secure processors, with ownership of multiple critical infrastructure IPs including secure boot, interconnect, and memory subsystems. Involved in bring-up. Responsible for functional, security-aware, and system-level verification in a production-grade SoC environment.
Verified an ultra-low-power RISC-V CPU for a smart energy-meter SoC, covering core micro-architecture, interconnects, low-power modes, and bus protocols using UVM-based constrained-random verification. Focused on power-aware verification, clock-gating, reset sequences, and system bring-up.
Led and mentored a 10-member engineering team to design and verify a high-performance RISC-V processor from scratch, covering advanced computer architecture and organization, micro-architecture, RTL, and verification. The program included: Design and verification of multiple ISAs and micro-architectures including RISC-V, x86 (IA-32 & IA-64), Y86-64, and LC-3 Implementation and study of operating systems including xv6 for CPU and memory-system validation Design and modeling of a GPGPU architecture and heterogeneous compute subsystems End-to-end CPU pipeline, memory system, and execution-unit design, supported by RTL and UVM-based verification Delivery of architecture labs, projects, and mentoring for engineers working on processor design and verification.
1. RISC-V processor verification(RV32/64 bit) (a) unprivileged and privileged spec. (b) Newly added extensions (c) Mode switching(M/S/U) (d) Memory sub-system(Caches, TLB, MMU) (e) Virtualization and Memory protection. (f) RISC-V Toolchain & environment.