Eindhoven, North Brabant, Netherlands
After obtaining my Ph.D. working for four years as device physicist in NXP Semiconductors studying MOS transistor mismatch, I joined ASML B.V. as application and business support engineer. Among my responsibilities there are customer support, consulting activities for process improvement and new product introduction. Specialties: Device simulation, electronic device physics, statistical analysis, customer support, new product introduction, people management.
Within my department we manage all customer support aspects (new product introduction, install base management, application and equipment support, upgrade, install and relocations, cost management) of the ASML metrology tool called Yieldstar.
Besides my technical contribution as application engineer mainly towards the BL Apps of ASML I also lead a team within the Customer Support (CS) application imaging group. Among my responsibilities there are: people management (end of yer review, career development), resource allocation help to the group leader, supervision of escalation progress and coaching of team members.
Two supposedly equal transistors are always microscopically different. Line edge roughness, oxide thickness variations and random dopant fluctuations are the main causes of intrinsic parameter fluctuations in Nano-CMOS devices. As the devices become smaller, these fluctuations increase and, if underestimated, they may lead to low performance or even to circuit failure. Causes and effects will be studied for current and future technology nodes using advanced simulators and characterizing test structures properly designed. Our goal is to deeply understand those causes in order to improve process technology and extract a general model of statistical variations suitable for circuit designer. This project is carried out at NXP Semiconductors Research in Eindhoven (NL).
Six months project to build a measurement setup for mini array of phase change memory. The project included also evaluation of phase change memory performance.
Master thesis on electrical characterisation of SiC and SiN CVD layers as passivation on high resistivity silicon substrates.