Greater Boston
I am experienced in matters concerning finance and technology. I have performed research and analysis in support of economic testimony in a range of finance and antitrust litigation. I have supported experts in their preparation of reports and testimony related to the 2008 financial crisis, including residential mortgage-backed securities loss causation and damages assessments, and have developed damages exposure and mediation-related analyses. I have significant experience in settlement benchmarking and fast-paced quantitative negotiation. In addition, I have offered testimony on damages analyses related to mortgage-backed securities. I have worked on several oil and gas bankruptcies, including recent matters evaluating the reasonableness of oil price forecasts underlying restructuring plan feasibility analyses. My antitrust work has involved semiconductor manufacturing systems and practices, credit card exclusionary rules, and telecommunications including the modem chip industry. I have particular expertise in computer hardware and securities. My role at Analysis Group involves translating qualitative questions into quantitative problems, and solving them. I build and lead diverse teams of analysts, MBAs, and PhDs who work with industry/academic experts and clients to identify, frame, analyze, and solve complex business, technology, and finance problems. I'm always interested in talking. Contact me at peter (dot) finch (at) gmail (dot) com or peter (dot) finch (at) analysisgroup (dot) com. Keywords: computer hardware, computer software, oil, gas, LNG, technology, settlement benchmarking, simulation, investment, corporate finance, bankruptcy, Chapter 11, restructuring, structured finance, mortgage, MBS, M&A, strategy, semiconductor, manufacturing, fabrication, microprocessor, server, ASIC, CPU, GPU, I/O, modem, AP, CDMA, LTE, model, statistics, big data, forecast, algorithm, regression, data analytics, financial analyst, consulting, data science
Build, lead, manage, and work as part of broadly-skilled teams of analysts, MBAs, PhDs, and industry/ academic experts to solve complex business issues. Employ rigorous, original research and analysis, typically in the context of multi-billion dollar and high-profile litigation. Grow and manage teams analyzing large volumes of data, developing software, and developing sophisticated statistical models; analyses are efficiently and effectively implemented. Support attorneys and academic experts in all phases of litigation and mediation from pre-trial discovery, exposure analysis, and strategy to expert reports, deposition, and trial preparation – all subject to tight deadlines and discerning, sophisticated, and demanding clients. Manage effective communication between team members, clients, external counsel, and industry/ academic experts to ensure all parties are engaged; requisite information, interviews, and data for analyses are obtained. Results are relevant, robust and understandable. Concurrently manage multiple consulting projects generating multi-million dollars in annual revenues. Train new analysts and associates in quality standards, teamwork, and technical skills. Develop, motivate, and mentor internal team members to foster sense of teamwork and individual ownership.
Launched startup hedge fund during second year of MBA program. Built quantitative models to support FX trading system using carry, momentum, and proprietary strategies. Built data and trading infrastructure using Bloomberg tools, MATLAB, Visual Basic, and Bear Stearns Prime Brokerage trading software. Recruited from MBA internship on State Street FX desk by departing MD.
Led performance modeling and verification efforts for the development of large computers. Specialized in reliable, high-performance IO (e.g., proprietary networks, PCI-X, PCI Express, and Infiniband bridges and switches) and memory systems (e.g., high-end DDR3 memory). Wrote large multi-threaded hardware simulations in C++ and Vera, including system-level many-ASIC, many-microprocessor (24 – 384) cycle-accurate models running on massively parallel hardware. Debugged Verilog at the module and ASIC level, including finding an important routing consistency problem in interconnect fault-tolerance architecture before chip release to manufacturing.
Developed methods for selecting representative segments from large benchmarking programs using hardware instrumentation and statistical techniques, as part of thesis research supervised by Professor Arvind at MIT. Researched alternative sorting methods for use in the C++ Standard Template Library (STL). Work influenced the evolution of the STL standard.