Waltham, Massachusetts, United States
Experienced, R&D oriented PhD level digital integrated circuit designer. Deep expertise in FPGA architecture and CAD, and broad experience across all aspects of digital circuit design from concept to first silicon test.
Chief architect of FPGA chiplets. Develop automation techniques for end-to-end flow of FPGA circuits from high level description to GDSII format. Enable turnkey implementation of FPGAs and associated CAD support for RTL-to-bitstream flows required by FPGA end users. Lead other engineers in development of all hardware and software models required to productize FPGA chiplets.
Co-lead multi-organization team performing government sponsored research developing pre-silicon side channel analysis vulnerability detection software and related ASIC design tasks. Present work to research program sponsors. Mentor junior engineers. Work with company business development teams to market ASIC design R&D capabilities. Develop technical volume content for R&D grant proposals.
Lead government sponsored research programs developing electronic design automation (EDA) flows for quantifiable assurance of integrated circuits.
Technical Lead, DARPA ReImagine program. Along with program managers, lead a team of six engineers developing invention of field programmable imaging array (FPIA). Train hardware lead in architecture of FPGAs integrated with image sensing hard macros. Train software lead in adapting open source FPGA CAD software to meet FPIA requirements. Define FPIA use model and develop example applications serving as tutorials. Present technical data to program sponsor and program peformers. Assist group and division management in development of future programs in semiconductor and superconducting circuit design and electronic design automation (EDA). Patent applications in progress for DARPA ReImagine activity. Previous projects included: Lead EDA support and digital design activities supporting research in cryogenic CMOS circuits. Lead internally funded continuation of Ph.D. research, including design, fabrication, test, packaging, and PCB board integration of subthreshold FPGAs. Lead other staff in development of process design kit (PDK) for novel Lincoln process technologies. Design and characterize standard cell libraries for near-threshold and subthreshold operation. Design and fabricate test chips for novel process technologies fabricated at Lincoln. Perform design studies for ultra-low power digital circuits for biomedical, cybersecurity, and RFID applications. Present research results at conferences.
Fabricated subthreshold FPGA test chip with record-low single supply voltage operation of 0.26V. Performed the first multi-benchmark minimum energy analysis study of FPGAs in simulation with novel CAD tool flow. Published results in IEEE journal.
Lead designer on three readout integrated circuits (ROICs) for use in advanced imaging systems. Write FPGA firmware for ROIC control used in first silicon test. Design and verify ICs using Cadence, Mentor EDA tools. Write documentation, hold design reviews.
Participate in design, verification, and production-test bring-up for high-performance 8-bit microcontrollers. Implement feature enhancements and bug fixes on product family RTL databases. Support test engineers in debug of production test vectors. Use test boards and software to debug silicon functional behavior and verify power requirements are met. Design, debug, and write documentation for test logic on 8-pin microcontroller.