Germany
Automotive Microcontroller Chip Integration/ Development Physical Design flow development and Automation for Physical Design Integration of SoCs
Performance Evaluation and Analysis Framework (PEAF) - Silicon Architecture AECG Evaluating future generation NoC architecture while influencing NoC compiler for current generation Versal devices. Redefining the routing phase of NoC compiler by introducing linear programming based constraints and showing bandwidth improvements.
1. Enabled Tensilica HiFi DSP support on Eigen Library by mapping PacketMath functions to target SIMD ISA, delivering significant performance uplift. 2. Improving out of the box performance of various single, double precision floating point benchmarks on Tensilica HiFi DSPs, devising auto-vectorization.
1. Suggesting ISA improvements and showing improved energy and cycle numbers for speech/audio software coding systems like SBC, Opus by optimizing them with the help of Tensilica DSP core's VLIW, SIMD and FLIX bundling capabilities. 2. Optimizing various digital signal processing kernels from Tensilica NDSP Lib for new HiFi DSPs. 3. Exploring and Optimizing NN kernels, Tensorflow (TFLM) based NN operators for HiFi DSPs. 4. Generating golden reference for neural network accelerator work loads. 5. Optimizing ARM-CMSIS library kernels on Tensilica HiFi DSPs.
Analyzing Facebook's Voiceloop Text to Speech converter to port on Tensilica HiFi DSPs.