Santa Clara, California, United States
Graduated with Master's in Electrical and Computer Engineering at Purdue University in West Lafayette, Indiana specializing in VLSI and circuit design. Self-motivated and dedicated engineer with 3+ years of design, development, and debug experience in the semi-conductor industry. I have worked as a software/firmware developer for power management and control in the semiconductors industry. Skilled programmer (C, C++, Python, assembly) with knowledge of ARM, Tensilica and Foxton architectures. Proficient in tools like NI LabVIEW, Matlab & Simulink, JTAG/Lauterbach, Altera software tools (Quartus, Qsys, Nios2 IDE) and Altera FPGA board. My areas of interest include computer architecture, power architecture, embedded firmware/software development, SoC design and verification.
Design and verification of low power features for discrete and integrated GPUs.
Developed mechanism to auto-generate network graphs to understand co-authorship, location and publication areas for Institute of Sustainable Future at Purdue University.
Leakage modeling to estimate leakage at various voltage/temperature/part-type and generating power scaling factors from varied Pre-Si and Post-Si sources. Process dependent/independent parameter modeling for different workloads.
Formulated a methodology and built a tool for auto generation of SoC register address map, its collaterals like C headers, register models, UVM RAL models and testcases to check the generated collaterals, significantly minimizing IP level DV effort.
- Curating data, development, and test of Purdue University Research Repository (PURR) database software in the Distributed Data Curation Center (D2C2), Department of Libraries and Information Science. - Mentored the class of Introduction to Data Lifecycle Management (ILS 103) as a graduate teaching assistant.