San Jose, California, United States
Currently at Etched, working on advanced power modeling and infrastructure for next-generation AI hardware. Previously led power architecture efforts at Nvidia and Qualcomm, spanning GPU power budgeting, thermal-aware implementation, and interconnect optimization. Developed scalable methodologies and automation flows for full-chip power analysis, collaborating across architecture, design, and CAD teams. Proficient in PrimePower, PowerArtist, Joules, PowerPro, and scripting with Python and Perl. Focused on enabling energy-efficient, high-performance silicon through data-driven design and cross-functional engineering.
• Led the PPA strategy for AI inference ASICs, focusing on maximizing performance per watt • Developed power models to assess architecture and implementation trade-offs for LLM inference workloads • Collaborated with Arch, Design, and Implementation teams to establish power-efficient design methodologies
• Developed power models for multiple GPU units across architectural and post-silicon simulation environments • Conducted detailed GPU power analysis and drove optimization initiatives to improve energy efficiency • Contributed to the architecture and implementation of low-power features like clock gating and rail gating • Executed critical chip-level gating ECOs to enhance power efficiency and meet design targets
• Responsible for power sign-off and power budgeting of all mobile GPU cores • Lead for all thermal-aware implementation initiatives • Led major power optimization efforts with multi-disciplinary teams