Oscar Sanchez

FPGA/Digital Designer

Paris, Île-de-France, France

About

Experience

  • Senior Software Engineering at AMD
    Aug 2023 - Present · 3 yrs

    Hardware accelerator design based on FPGAs and processor arrays for AI applications

  • Architecte FPGA at Mipsology
    Jan 2019 - Present · 7 yrs 7 mos

  • R&D Engineer at BOWEN-ERTE
    Aug 2013 - Dec 2018 · 5 yrs 5 mos

  • Postdoctoral Researcher at IMT Atlantique
    Mar 2013 - Aug 2013 · 6 mos

    Channel coding algorithms for 5G communication systems

  • Ph. D. Student at IMT Atlantique
    2009 - 2012 · 3 yrs

    Design of channel decoding architectures for high-speed communication systems. Architectural solutions for high throughput turbo decoding. Solutions to break the bottleneck in serial iterative decoding algorithms.