Bengaluru, Karnataka, India
Memory Controller (HBM3) , Core Harding for Neural Engine , Tablet , Wireless, Graphics ,Computation and Automotive processors.
I will be focusing on the NEX portfolio Projects.
I was working on the Intel Auto based products. Here My focus was on Product and industry Requirement standardization for Automotive segment, I have also worked on the IP Configuration and Harding aspects. Team Augmentation , SD end to end Implementation along with all Signoff would be Primary
I have been a part of HPG-INDIA Group for more than 6 years. I was responsible for End to End Closure in Physical Design at Sub-System Level. In HPG my project portfolio includes product like HBM3 Subsystem , Mobile Cores , VPU Neural Core , Processor IP implementation, Type C protocol implementation, Modem IP cores.
I was part of part of Graphics Core Group in Qualcomm. I was involved in the implementation and integration of graphics cores for snapdragon series.
I have worked with Synapse Design Automation as a Lead Physical Design Eng. I was for responsible entire physical design implementation task and customer delivery. I have contributed in mentoring other PD teams, internal projects and also handle a small teams • Project with Juniper Networks : Network Processor chip in 28nm. • Project with ST Wave Div :Multimedia chip in 28nm.
I have worked as a Sr.Physical Design Engg in RF and Sensor group in Freescale. I was leading the back end activity for stack die implementation for MEMS based sensors (accelerometer, magneto meter). I was completely responsible for all back end activity,chip assembly, working with TSMC Fab and Post tapout activity.
I have worked in Physical design domain for automotive products in ST as a senior Design Engg. I was involved in Full chip physical design for micro-controllers, GPRS and Multimedia implementation in 40nm/55/65/90/130nm technology. I was mainly involved in Feasibility Study, Assembly rule check, Floorplaning, Power planning, Congestion analysis, Placement, Timing, CTS, Routing,Physical verification, and chip aasembly.