San Jose, California, United States
ASIC & FPGA design for AI acceleration, GPU, Machine Learning/Deep Learning systems. Coursera deeplearning.ai specialization 5 course series, Stanford ML/CV courses
AI acceleration ASIC Design
GPU micro-architecture, design, modeling, verification, physical design, PPA
Augmented Realty (AR) Graphic IP & GPU micro-architecture, design, verification, modeling, performance/PPA
Neural Network Processor ASIC architecture/micro-architecture, design, verification and implementation, performance/power/area trade off analysis, low power, high speed (2 GHz+); GEMM, LLM, transformer, high performance computing systolic array, tensor, fused QKV, flashattention, tiling, KV compression, embedding, Norm, softmax, on-chip networks, memory, HBM, Tensorflow, Keras, Numpy, Python; VCS, Lint, CDC, formal verification, synthesis, Floorplan, STA, ECO, test plan, UVM, coverage, assertions, HLS, HW/SW co-design, FPGA emulation, system fast prototyping, performance modeling, C++/Python, lab bring up, firmware Deeplearning.ai 5-course specialization, Coursera Machine Learning course, Stanford CS231n CNN for Visual Recognition, CS224n Natural Language processing & CS229 (Machine Learning), MIT 60001 Python programming deeplearning.ai specialization course mentor
High-speed transceiver subsystem silicon design, PCIe, 10G/25G, 40G/50G/100G Ethernet, Design Development, Project management, Product management, Customer support
PCI Express Gen1/2/3, IO Virtualization, DSP (fixed point and floating point IEEE-754), 10G/40G/100G Ethernet, Interlaken IP definition, development, verification (OVM/UVM), physical implementation, applications in 20nm/14nm FPGAs, hardware emulation, HLS
Taped out 90/65/45/28/20nm FPGA families, high-speed I/O, DSP, FPGA control block, DDR IP and subsystems