Dhanbad-Ranchi Area
Namastey! 1.> Designation skills :: I have Designed & Simulated MIPS 32-bit Pipelined processor using Vivado. I have done MATLAB program for the Pioneer P3DX robot with 360° obstacle avoidance using all 16 ultrasonic sensors in CoppeliaSim. I have keen interest in S.V. & UVM & AMBA & UPF & GLS & SoDs. I have done many projects in embedded microcontrollers. I have done Assembly language project in visual studio for MASM8086. I have done designing of a 5:32 bits DeMultiplexer. I have made 3.5mm audio jack upgrade to USB project. I posses all repairing knowledge of Laptops both hardware and software including soldering. I have done FPGA projects like Digital Filter design. I have done Smart Energy Meter project. I have done automation with Python using PANDAS and NumPy and re(Regular_Expression). I worked on Airlines-Demand-App using API avaiationstack.com(Check my GIT hub). demo:: https://drive.google.com/file/d/1Y0oYPfnkD2yAt0RlVI3Lg0SSB5cJAMfq/view?usp=sharing 2.> Software skills :: I am well acquainted in using kernel LINUX and O.S.->UNIX/MS. DOS I know to use ClearCase/Xilinx/Vivado/MATLAB/GVIM/IDE=Keil uvision/uTorrent/PSpice/Visual Studio/Tor Browser/KiCAD 3.> Programming skills :: "GitHub Link = https://github.com/laptopcomputermistri/" language = TCL/C/C++/Shell_Script/Perl/Python(NumPy,PANDAS,Matplotlib,Django,requests,tkinter) ***Suggestion Daily Run atleast 1 one program on HackerRank(455/2305::Gold), Programiz PRO, CodeChef, Python Principles, Edabit, freeCodeCamp, 101computing, Codecademy, GitHub*** -> 45 mins. 3.1> Efficient in using AI tools like Copilot, GitHub Copilot, Colab, ChatGpt, Perplexity, claude.ai 4.> Financial skills :: I was a regular Stock Market Intraday equity/options trader. My loss was 50 lakhs. "Remember, Future-Options trading has NO future and there will be No option.". Stock Market is a well that can engulf whole country. Be safe! and stay away. https://docs.google.com/spreadsheets/d/1iRlV8dg3Mu9p-lQbjvDnRe41CvhI9hZ46Nb7u2Bj_Cw/edit?usp=sharing 5.> Publications :: I have 3 Three publications. I was working on 1 one more publication "NIKHIL-SANATAN Law ::" I also solved Optics derivation in details. Thanks!. Yours Sincerely NIKHIL eMail = [email protected]
Making projects/assignments for Indian as well as foreign students. Serving in Europe/Middle east/America through academia.
Taught B. Tech. ECE.
SoC Design Verification Engineer was my current Position. I worked in Computer/MSM(mobile) projects. I learnt everything from scratch. I verified Audio AI subsystem known as LPASS. My favorite part was verification of WSA(Wireless Speaker Amplifier) verified with VIP(Verification Intellectual Property) in both RTL and PARTL. I developed an automation Python script which input .xls/csv input from IPCAT -> and using datas such as GPIOs number/Register name-address -> update Driver in C and S.V. files of Baseline for Testbench. I also learnt the Test generation methods from QSAM and created new test for delta features addition/FUSE verification by modifying files .sln/.csv. I also learnt about Toggle coverage and SVA i.e. assertions. I understood the Class, Object, Method, Inheritance, Polymorphism, inbuilt functions(super(),__init__()), Indentation. I understood UVM hierarchy and classes. I used TARMAC/Tracker/Waveform/.axf<-ASM instt. for debugging. Steps involved writing/reading in known location such as DDR/TCM/Cache and matching the datas with desired response. I worked with 3 three procs namely APPS/RPM/Lpass Q6. In tests 1 proc was primary and other usually lpass secondary. The RPM/APPS was mainly used boot the secondary processor(after building the environment i.e. test bench in test Run phase). Before actual test run starts i.e. in alt_session.log phase the .axf files i.e. hex got loaded in the TCM of secondary proc. Now, finally in session.log Test got executed. GVIM editor was used for debugging/pattern searching. Some LPASS tests (particularly WSA(VIP) involved loading of .hex file execution during run time. We used to getting them from core DV team. I was in SoC simulation.). There were 3 three category of tests for LPASS namely CODEC/VIP/basic RTL. I used to be working more than 16 Hrs daily. It was also projected that in 2026 AD, I would have been promoted to Senior engineer.<- But, this was Not in my destiny. Till 29 January 2025, I worked in Qualcomm.
I worked here in SVE BDC-NDC Peripherals for UFS(Universal Flash Storage). I validated for MSM project mobile namely POCO M6 Pro 5G with storage 256GB. Lauterbach tool was used. Perforce was also used(CI/CD pipeline). Using VNC I understood the remote login process to Windows machine as Lauterbach works on MS windows. via JTAG, Machine was connected with PCB Board. I also took Power and Performance measurements in laboratory. I saw the Snapdragon Chip mounting on bench(dock). There were trays/rack issued for particular block(UFS/LPASS/TURING etc.) or mainly projects such as Netrani/Clarence/Hamoa/Palawan. Lanai used to be base project(used to join a project via mailing List -> go/soccommit(Design review pages for delta features)+LINUX accesses). I also used to be updating Confluence pages. There used to be different LINUX servers(cluster). I was accessing Tiger(Bangalore)/SD(San Diego)/Zhu(Taiwan)/GRIDSDCA/GRIDECDB(or A). I used to go to laboratory to Reset the board during faults in validation process. In validation LINUX is used to build the tests. The process is same as of verification but combination of practical and controlled environment for chip or [RUMI(emulation)==FPGA]. As SoC depends on different subsystems(IPs). updated Driver(Driver is a file where we actually give inputs to Register(32 or 64 bits). They are written in C or C++ or S.V.) was released in various phases (SiQ1 for SVE and Q0,Q1 for Verification). Based on all releases, after processing TCL commands in LINUX a combined test was generated of which the path and file was loaded in Lauterbach from unmanaged area. I also saw working/debugging of QSPI/I3C/PCIe. Remark- NoC uses AMBA protocols & APPS<->DDR, chi-protocol, LPASS uses MIPI SoundWire/I2S communicate with speaker or Tambora. There were other teams also like P.D.(Physical Design)/STA/CAD/GPU. In SoC DV the last project I worked was on Glymur/Glymur v2/Mahua. All worked coherently to make -> Snapdragon® X Elite is the processor(laptop).
Skill Development in India
Web Mining.