Raleigh-Durham-Chapel Hill Area
Digital logic design engineer with 15+ years of experience across microarchitecture definition, RTL implementation, and multi-generation tapeouts, with a career-long focus on the boundary where hardware and software meet. Most recently at Nvidia, where I spent seven years as a senior ASIC design engineer on a core GPU rendering unit through multiple product generations, followed by a platform architecture role doing compiler validation and LLVM toolchain development for a custom 7-wide VLIW embedded processor. Before that, seven years at Juniper Networks included full block ownership from microarchitecture through tapeout, and several years building cycle-accurate and transaction-level performance models in C++ and SystemC. Earlier experience spans the full hardware lifecycle: FPGA and board-level product development, post-silicon bringup and characterization, and CPU design verification at AMD on the Bulldozer x86 core. Graduate research at Georgia Tech on parallelizing workloads for the IBM Cell heterogeneous processor. On the side, I've founded and operated several small technical ventures -- the most notable being an early social networking site that reached over 1 million registered users before the rise of Facebook. Now targeting roles in hardware/software co-design, CPU/GPU performance architecture, ML accelerator performance engineering, or related crossover roles leveraging deep hardware insight on the software side of the interface. Core skills: Microarchitecture Design, Performance Modeling (cycle-accurate / transaction-level), C/C++, SystemC, Python, RTL/SystemVerilog, ASIC Design, Hardware/Software Co-Design
* Hardware/Software Co-Design in support of PVA [Programmable Vision Accelerator] -- a heterogenous RISC microprocessor + custom ASIC accelerator SoC subsystem for low-latency/high-efficiency Computer Vision acceleration * Development and support of flows leveraging Verilog RTL/SW autogeneration of fixed-function and programmable accelerator logic for integration into PVA accelerator functions * Architectural tool development, including C and C++ compiler development and developer support for the custom heterogeneous 7-way VLIW SIMD co-processor in the PVA subsystem on NVIDIA Tegra systems. Driving these tools towards ISO 26262 Functional Safety and Resiliency tools certifications for automotive and ADAS (driver-assistance) applications.
* Digital design, microarchitecture exploration, RTL implementation, timing closure, and low-power design improvements on a critical, core graphics rendering unit (ROP/ZROP) for Nvidia's primary GPU products. * Multiple successful tapeouts contributing to 4+ generations of multi-billion-gate ASICs for the company's primary GPU and enterprise HPC/ML/AI/DL accelerator products. * Significant impact on the graphics ROP units, including moving an actively developed unit with a decades-old codebase to a new chip partition, and transitioning that memory-intensive unit from the physical to virtual address domain * Implemented low‐power ASIC design optimizations using a multi‐level clock gating scheme. Used Formal Verification techniques to prove functional correctness, modifying the logic to facilitate full formal proof closure * Adopted Deep Learning methodology to monitor and optimize the random regression stimulus to steer nightly regression test selection towards leveraging the most impactful configurations to achieve high functional coverage, while minimizing run-time and simulation license usage * Expanded chip-wide cross-functional improvements in chip register definition and linting – improving consistency and functional correctness, while finding and preventing critical security vulnerabilities * Developed, implemented, and executed a methodology to run the full unit regression suite on the production gate netlist. Discovered a bug in Synopsys VCS critically impacting this effort, and drove to resolution with tool vendor
Founder and principal technical and business direction for a series of successful micro-startups and entrepreneurial ventures
Founded, led, and operated a profitable datacenter-scale data/compute processing venture with 3 partners, scaling to $300k+/year revenue in just its second year, before being edged out by larger players * Implemented and deployed custom device firmware optimizations in C for 30+% net perf/Watt gains over stock OEM configuration * Responsible for primary vision and direction, procurement of servers and equipment, negotiation and contracts for colocating 5 full 48U cabinets of equipment in a tier-1 datacenter * Managed physical installation, implemented and maintained network infrastructure, deployed custom software monitoring systems
Operated a successful and profitable bitcoin mining pool system using a custom developed algorithm * Custom algorithm implementation yielded a 25 – 40% improvement in earnings from the same hardware, by leveraging the time-based differences and inefficiencies in reward schemes between roughly a dozen different primary bitcoin mining pools, via frequent switching between pools based on instantaneous optimal profit. This improved efficiency attracted dozens to hundreds of concurrent users * This effort contributed to a wider industry shift in incentivizing the vast majority of bitcoin mining pool operators to switch to more universally fair/proportionate and “pool-hopping-proof” reward algorithms Tech stack: multithreaded Perl application for algorithm implementation and work distribution to client connections | MySQL | Bitcoin Core / Blockchain (no relationship to the current service/website which goes by the name "MultiPool")
Unit lead/owner, performing MicroArchitecture Design and coordinating RTL Implementation with the design team implementing units on the primary ethernet WAN datapath of several generations of next-gen high-performance ethernet ASIC routing chips. * Technical unit lead and block designer through 3 generations of next-generation routing ASICs -- leading, providing technical mentorship, and coordinating tasks among up to 3-5 engineers in both RTL implementation and unit verification through silicon bringup * Developed microarchitecture for a new unit which interfaces with offchip memory controller, re-orders and re-packs memory read responses, and steers full-data Ethernet packets towards 50+ configurable interfaces at full line rate of 1.2 Tbps aggregate bandwidth * Responsible for full unit lifecycle through synthesis, physical design, timing closure, and multiple successful tapeouts * Mentored junior engineers in functional verification, code coverage and coverage closure, and digital design/debug * Pioneered the methodology for adopting a full-fledged IDE for SystemVerilog development with context-assist – despite proprietary inline scripted Verilog language extensions – driving productivity gains for 50+ engineers across multiple sites * Developed a widely-adopted methodology for improved source code management, leveraging a git overlay to the outdated central code repository for better collaboration, code-sharing, development, and lightweight branching
* Implemented extensive behavioral, transaction-level, and cycle-accurate software reference models in C++ and SystemC for ASIC unit verification and architectural modeling * Developed multiple from-scratch block-level verification environments in C++ / SystemC, from block functional specification through verification strategy, testplan design, testbench architecture, and execution – leveraging UVM principles * Served as unit verification owner for two separate design blocks across 3 full-lifecycle projects, leading verification teams of 2-3 engineers. * Successfully verified both the host and receiver interface blocks for a reliable high‐speed serial interconnect (“GCI”) to a proprietary low‐latency memory chip, as well as the several design variants used on the 3+ host chips in the product family. * Gained extensive implementation knowledge relating to the PCS, data link, and transaction layer for the GCI memory interconnect by working closely with the unit designer. Implemented several RTL bug fixes. * Designed and implemented verification tests and testbench on the main datapath for a successor high‐bandwidth network processing chip, while meeting aggressive timelines as the only from-scratch unit and testbench on the chip * Through careful modeling and close attention to detail – discovered a previously-undetected latent bug in the common design interrupt macro used in every block for the then-current chip, plus prior 3 generations of productized core routing ASICs * Eliminated redundant test writing for full-chip verification by collaborating closely with Chip Verification Lead to design and implement a methodology which reuses block‐level tests in subsystem and full‐chip verification
* Full product lifecycle ownership of a switch for a proprietary sensor network; plus a TCP/IP Ethernet bridge for remote access. * Drove and implemented the product starting from whiteboard concept through board design; component selection and sourcing; PCB layout including 300+ pin FPGA; coordinating board manufacture and assembly; RTL logic design and implementation for the FPGA; prototype bringup; and product manufacture. * FPGA logic design and implementation of the full switch logic, including I2C interface to Ethernet module.
Functional verification, test development in C++, and RTL debug on the Decoder unit of the novel Bulldozer x86 CPU