Austin, Texas, United States
Logic Design Engineer with experience in IP and SOC logic design and verification. Strong skills in SOC build flow and methodology. Proficient in VLSI front-end design flow and strong knowledge in back-end flow. Specialties: • Micro-architecture, IP and SOC design. • Clock domain analysis, logic partition, LEC • Synthesis, static timing analysis, floor-planning, timing closure, CPF flow. • Simulation, gate-level verification, gate-level ECO. • Shell script, Perl, TCL, and Verilog RTL. For new opportunities, please contact me via email: [email protected]
I am a logic designer working on IP development and SOC design for Digital Networking products.
Logic Design Engineer worked on multi-cores networking SOCs
Logic Design Engineer worked on Broadcast Digital Subscriber Line (BDSL) MAC layer.
Networking processor logic design. Designed In-Circuit Emulator (ICE).