United States
I have extensive experience in semiconductor process development, equipment maintenance, and research. For over two decades, I have focused on semiconductor manufacturing, process optimization, yield improvement, and advanced materials integration. My work encompasses process optimization from 45nm to 7nm process nodes, EUV lithography, and 3D integration technology research.
Leading research in advanced semiconductor materials and process integration for next-generation logic devices. Focus areas include gate-all-around (GAA) transistors, 3D integration, and novel interconnect solutions. Collaborate closely with cross-functional teams from academia and industry to accelerate technology transfer from lab to fab. Regularly contribute to technical reviews, design of experiments (DOE), and process development strategies aligned with roadmap targets.
Conducted research on EUV lithography, novel etch chemistries, and high-k/metal gate integration. Contributed to breakthrough process modules for sub-5nm nodes. Delivered technical insights supporting patent filings and conference publications.
Directed cross-site process improvement initiatives for leading-edge nodes (e.g., 7nm, 12nm). Partnered with R&D on new materials integration and lithography optimization. Mentored junior engineers and led benchmarking efforts with external foundries.
Led process development and troubleshooting initiatives for FinFET and SOI technologies. Drove continuous improvements in cycle time, throughput, and yield. Collaborated with global engineering teams to implement best practices across multiple fabs.