Santa Clara, California, United States
I have 3+ years of experience in the VLSI industry and have worked on the entire Digital Design Flow of ASICs(RTL Design to GDSII). Currently I am pursuing my Master's Degree in Computer Engineering at UC San Diego and want to further my career in design and modelling of CPUs, GPUs and custom accelerators.
Teaching assistant three quarters courses for following courses - ECE 111 - Advanced Digital Design Project (Winter 2022) - CSE 140L- Digital Systems Lab (Spring 2022) - ECE 111 - Advanced Digital Design Project (Winter 2023) Responsibilities: - Taught basics of system design using Verilog to students - Took office hours and lab lectures to clarify doubts and guide students with their project - Grade all assignments/projects and help with logistics of the course
Working on the command processor of GPU for flagship SoC Performance evaluation on existing benchmarks for identifying register access pattern and bottlenecks
As a digital designer at TI, I developed ASICs for Medical product line with complete digital ownership from Architecture, RTL to GDSII. My responsibilities included: 1) Developing the digital specification along with the field engineers for DSP applications 2) Modelling and implementing RTL for the control path and data path 3) Ideating memory subsystem architecture for efficient streaming of data in beamforming applications 4) Verifying all the IPs I wrote using golden vectors generated through Python/MATLAB 5) Synthesis and Backend of SoC