San Francisco Bay Area
I'm currently a CPU RTL Design Engineer at NVIDIA, Santa Clara, working on Instruction Fetch. I have a Master’s in Electrical and Computer Engineering (Integrated Circuits & Computer Architecture) from the University of Texas at Austin and worked at Samsung Austin R&D Center (SARC) in CPU design for a few months. For my Master's thesis, I did co-op at AMD Research, where I worked on the stability bounds for reduced precision for Neural Networks. In summer 2018, I interned in the SoC Physical Design team at Apple Inc., Cupertino, where I worked on the implementation of an SoC IP block and power optimization methodologies for ultra low-power mobile SoCs. Previously, I've worked as an ASIC Design Engineer in Design-for-Testability (DFT) domain at Texas Instruments, Bangalore, India. My prime interests are CPU Architecture and Microarchitecture and System-on-Chip Design.
Part of the CPU RTL Design team, currently working on Instruction Fetch
• Part of the Globals RTL team responsible for power and clock management architecture and micro-architecture for CPU • Implemented logic for measuring activities in CPU core and caches to enable power savings by DVFS and worked with power team to minimize idle power consumption by implementing coarse/fine-grained clock gating • Involved in front-end UPF creation and automated isolation/clamp generation and verification methodology • Assisted DV team in writing directed functional test sequences for verifying targeted parts of the design
Worked as a T.A. for the course EE 316 (Digital Logic Design) for Fall 2017, Spring 2018, Fall 2018 and Spring 2019, and developed the labs based on designing in Verilog and simulation on Basys3 Artix-7 FPGA board
• Stability analysis for neural networks to make the networks amenable to reduced precision and resilient to adversarial perturbations • Understanding various characteristics of deep neural networks by generating state-of-the-art perturbations which are orders of magnitude smaller than the network inputs • Evaluation of the methodology on various deep neural networks like AlexNet, VGG-19, CANDLE benchmarks, etc.
• Netlist to GDSII implementation of an SoC IP block using latest process technology, resolving congestion and IR/IVD challenges • Developed power optimization physical design flow methodologies for ultra-low power mobile SoCs