Mustafa Gencel

Engineer

Istanbul, Türkiye

About

Generalist senior software and senior hardware engineer (with technical leadership experience) with: - strong background in scalable distributed systems, parallel programming, data processing pipelines - strong background in CPU, SOC architecture and end to end verification(from test plan development and testbench architecture to functional and power verification) of very large scale chips - basic AI and machine learning algorithms and implementation knowledge and experience

Experience

  • Software Engineer at Microsoft
    Feb 2024 - Apr 2026 · 2 yrs 3 mos

  • Software Engineer at IS Investment
    Aug 2023 - Jan 2024 · 6 mos

  • Infrastructure Engineer at Citadel Securities
    Jun 2019 - Jun 2022 · 3 yrs 1 mo

  • Software Engineer at Google
    Aug 2017 - Jun 2019 · 1 yr 11 mos

    Google Cloud

  • Apple (7 yrs 2 mos)
    • Software Engineer
      Jul 2016 - Aug 2017 · 1 yr 2 mos

      Apple Maps Participated in development of multiple software projects, including: - large scale data processing pipeline in Hadoop and MapReduce - designing, developing and optimizing backend server features that serve hundreds of millions of people - creating regression, unit tests and automated testing framework to run these tests while taking AB tests and different branches into account - doing code review, build and deployment - creating build flow in CMake and Python for multi-language, multi-platform projects - creating CI flow for these multi-language, multi-platform projects

    • Verification Engineer
      Jul 2010 - Jul 2016 · 6 yrs 1 mo

      Extensive experience in: - end to end verification of ASICs - microprocessor and SOC architecture and programming - object oriented development and design in System Verilog/C++/Lua from requirement analysis to final implementation - test planning, performance testing, profiling, debugging and automation - video compression formats and algorithms Participated in verification of multiple ASICs from test framework development to tapeout, including following: - defining verification test plans and managing execution of these plans - architecting and implementing test frameworks in C/C++, Perl, Lua and System Verilog for hardware verification, driver testing and validation - developing drivers/tb environments in System Verilog, in C/C++ and in Lua for USB, DMA, SPI, UART, H264/HEVC encoder and decoders, coherent cache systems, coherent chip fabrics - developing, collecting and analysis of functional and code coverage - event based modeling of subsystems in C++