Greater Toronto Area, Canada
I have over 6 years of experience in characterizing SerDes on various high speed interfaces such as 100GBASE Ethernet, PCIe, and Intel's Ultra Path Interconnect. My experiences have included: o Utilizing VNAs, J-BERTs, Sampling and Real-Time Oscilloscopes to meticulously characterize and debug SerDes performance. o Applying problem-solving skills and analytical insights to pinpoint and resolve signal degradation, crosstalk, and other challenges. o Working seamlessly with other teams such as the design, firmware and HVM teams to ensure flawless hardware implementation from Silicon Bring-up to PRQ. I'm always interested in continuing to learn about advancements in SerDes design, validation methodologies, and industry standards.
Qualcomm acquired Alphawave Semi in December 2025
UCIe Firmware and Post Silicon.
o Validate high-speed 100Gb/s SerDes for 100GBASE-KR2 and CR2 standards. o Characterize transmitter and receiver performance, measuring Tx jitter, Tx equalization, RLM, SNDR, interference tolerance, and jitter tolerance. o Calibrated receiver test setups for interference and jitter tolerance using VNAs, sampling/real-time oscilloscopes, and BERTs. o Collaborate with firmware, design, and systems teams to optimize PHY functionality. o Debugged SerDes performance issues on customer platforms o Develop and maintain Python and MATLAB scripts for automated characterization. o Gained expertise in DSP-based SerDes, including partial response equalization, and MLSD.
o Part of the Design Engineering Group/MPE. Worked on validating mixed signal IPs (PLL/IO) for Intel's Xeon processors. o Bench-level characterization of the core FLLs, PCIe Gen5 (32 Gb/s), and UPI over PVT o Developed software scripts for bench-level automation of FLLs and PCIe/UPI SerDes using Python. o Worked on Jitter Tolerance for PCIe Gen5 and UPI using a Keysight BERT. o Worked on Squelch and UPI Jitter Tolerance calibration using a replica channel board, Oscilloscope, ISI board, BERT, and Network Analyzer.
o Worked on High Speed IOs at Intel's FPGA group. o Validated PCIe Gen4 (16 Gb/s), UPI (11.2 Gb/s), and ADCs & DACs working at a sampling rate of 64GS/s. o Validated Signal integrity using several metrics such as Tx jitter, eye diagram, lane skew, S-parameters, and bit error ratio. o Automated lab equipment such as spectrum analyzers, BERTs, oscilloscopes, thermal control, and development boards using python. o Utilized lab equipment such as VNA, Oscilloscope, BERT, Signal Generator, and Spectrum Analyzer. o Validated IP with functionalities including SerDes and data converters. o Brought up lab infrastructure for Silicon bring up and validation. o Preformed schematics review and PCB layout review using Orcad Capture and Orcad Allegro o Implemented and debugged a Low loss circuit from X-Microwave using power splitters and RF switches to automate the validation of ADCs and DACs. o Wrote a validation report for UPI validation.