San Francisco Bay Area
*Have 6years of experience in VLSI Physical Design & Implementation *Involved in multiple projects for different technologies *Worked in multiple partitions in PNR/singoff's for partitions with 600k to 5.5M instance count. *Involved in synthesis, Syn-signoffs, floorplan of single and multi-power designs, placement, clocking, routing and ECOs (Caliber & Timing) manually with minimum impact of DRCs in highly congested area. *Involved in power optimization techniques *Have good scripting skills in tcl,perl programming languages. *Excellent work ethics with strong analytical, problem-solving and troubleshooting skills.
Worked as physical Designer for over 6+ years.The role encompasses a blend of hands-on technical expertise, project leadership, and mentorship within the chip design flow. Expertise in synthesis,floorplanning,placement,CTS and Route along with the sign-off tools. Proficiency with industry-standard physical design tools (Cadence, Synopsys, Mentor Graphics) and related flows (RTL-to-GDSII). Experience with low-power design techniques, including clock gating, power gating, multi-voltage design, and UPF/CPF flows. Excellent problem-solving, debugging, and analytical skills. Strong verbal and written communication skills for effective collaboration and documentation. Experience with managing project timelines, deliverables, and tracking to closure.