Mostafa Ayesh

AMS Engineer | Ph.D. | Semiconductors | Technical Content Creator

Irvine, California, United States

About

Mostafa is currently a senior staff AMS design engineer in Marvell Technology. He holds Ph.D. and M.Sc. degrees in Electronics and Electrical Engineering from USC. He received his B.Sc. and M.Sc. degrees in Electronics and Electrical Communications Engineering from Alexandria University and Ain Shams University (Egypt) in 2013 and 2017 respectively. He was awarded the B.Sc. with Distinction with honors degree as well as being the valedictorian of his class. - 8 years of industrial experience in Analog, RF/mmWave, and Mixed-Signal design. - Led 5 tapeouts and contributed to 19 others since 2014. He became an analog-mixed/RF IC designer at Silicon Vision from Dec. 2015 till May 2017. Starting in September 2013, he was a teaching assistant at EECE, Alexandria University till May 2017. In 2012, he got an internship in ASIC division, Si-Ware Systems which is an independent fabless semiconductor company that provides a wide spectrum of product design and development solutions. His graduation project entitled "High-speed serial link transceiver for 10 GbaseKR standards using a 65 nm CMOS process”. He worked through many technology nodes, TSMC130, UMC65, TSMC65, TSMC40, TSMC28, GF16, TSMC N3 and TSMC N2. Mostafa is the recipient of the USC Viterbi Graduate School Annenberg Fellowship during 2017-2021, and the IEEE CICC 2019 Student Travel Grant Award. He serves as a reviewer for the IEEE Solid-State Circuits Letters, Symposium on VLSI Circuits, IEEE Custom Integrated Circuits Conference (CICC), IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), and IEEE International Symposium on Circuits and Systems (ISCAS). Fields of interest: High-speed serial links receivers, Low-power analog and analog-mixed integrated circuits, integrated circuits for communications (Baseband, RF).

Experience

  • Senior Staff AMS Design Engineer at Marvell Technology
    Nov 2024 - Present · 1 yr 8 mos

    COMPHY team Designing the industry's highest speed SERDES in the most advanced nodes (5nm, 3nm, 2nm, ...)

  • PhD Student Researcher at SRC Research Scholars Program
    Jan 2023 - Oct 2024 · 1 yr 10 mos

  • University of Southern California (Greater Los Angeles Area)
    • PhD Candidate
      Jan 2019 - Oct 2024 · 5 yrs 10 mos

      Electrical Engineering - Electro Physics branch. Research group: Mike Chen Analog-Mixed Signal IC Group Research interests: mmWave Transcievers, High-speed serial links, high-speed ADCs and DACs, Low-power analog-mixed integrated circuits and systems Major Classes: Analog-Mixed IC Design I Analog-Mixed IC Design II Communications Integrated Circuits and Systems (RF IC) Quantum Mechanics VLSI Design Processing and Semiconductors Fabrication RF Systems and Hardware Current GPA: 4.0/4.0 Ranked first in all classes.

    • Research And Teaching Assistant
      Aug 2017 - Oct 2024 · 7 yrs 3 mos

  • RFIC Design Intern at Qualcomm
    May 2023 - Aug 2023 · 4 mos

    Worked on application specific voltage regulators.

  • RFIC Design Intern at Qualcomm
    May 2022 - Aug 2022 · 4 mos

    Worked on Debugging, Verifying RF systems. Worked on a design for an innovative wireless receiver front-end. Achieved 7/7 in career readiness.