United States
ASIC engineer focused on efficient AI-accelerator design.
Building chip for superintelligence
• CXL based memory tiering • Computational storage solution • Smart SSD
• SOC design and verification of cognitive radio system for IOT solution • RTL design and verification of spectrum sensing system using SystemVerilog and MATLAB • Developing cloud infrastructure for IOT solution • Collecting, Processing and Visualizing of streaming data in cloud
• VLSI implementation of 5/3 Lifting based 2 Dimensional Discrete Wavelet Transform • Stochastic Modeling of Cascading Failures in Power Grid Networks