Essex Junction, Vermont, United States
- Technical lead for advanced semiconductor test architectures, supporting complex SoCs from early silicon through high‑volume manufacturing - Defined test strategies for 2.5D integration, HBM (High Bandwidth Memory), and multi‑die packaging - Led validation and production test of high‑speed SERDES and complex communication PHY IPs, including protocol‑based testing - Architected scalable ATE test solutions enabling parallel test, reuse, and efficient ramp to production - Partnered with design and DFT teams to influence testability, coverage, and observability early in the design cycle - Developed reusable test IP, automation frameworks, and datalog standards (STDF) using Java and Python - Supported silicon bring‑up, debug, yield analysis, and test program migration across multiple device generations - Acted as a cross‑program technical leader, mentoring engineers and coordinating test strategy across teams and vendors
- Principal Test Development on ASIC 2.5D advanced packaging products. Core focus on interconnect testing, repair, HBM array testing and repair as well as customer integration and development. - Principal Test Development on ASIC Multi-Chip Module products including base ASICs as well as LP/DDR4. - Principal Test Development on partial good test methodologies including custom system readable fuse configuration registers.
- 20 years industry experience in semiconductor test development, program development as well as quality and 3rd party IP debug. - 2018 GlobalFoundries CEO Award recipient- 2.5D New Product Introduction - Principal Test Development on GF ASIC 2.5D advanced packaging products. Core focus on interconnect testing, repair, HBM array testing and repair as well as customer integration and development. - Principle Test Development on GF ASIC Multi-Chip Module products including base ASICs as well as LP/DDR4.
- Test development, program development as well as IP debug and fail identification. - IP including HSS (High Speed SerDes), LP/DDR3/4 and HBM (High Bandwidth Memory PHY and stack) core testing.
- Test Team Lead for 14nm T1 qualification, responsible for test/stress schedule as well as priorities of test, stress and data analysis - Product engineer responsible for designs documentation, test specifications, stress conditions and electrical and physical fail characterization for new advanced FinFET process
Product engineering for next generation semiconductor technologies including 14nm and beyond.
o Primary owner for eDRAM on 22nm system cache memory controller, including test/spec development, yield analysis, failure analysis, system memory subsystem integration and product reliability o Responsible for development of array mapping techniques for BIST tested chips to allow detailed array mapping for test, system, field and reliability fails o Enabled automated characterization of eDRAM using offline characterization control. This allows detailed characterization suites to be carried out without real time input or requiring engineering interaction
o Worked with broad team responsible for eDRAM test development for IBM P and Z series processor caches in 45nm, 32nm and 22nm technologies o Implementation of test methods, system and test characterization, failure analysis, yield and reliability failure analysis o Primary ownership of 32nm technology and product reliability/qualification test programs, program development, fail analysis and closure o Enabled automated characterization of eDRAM using offline characterization control. This allows detailed characterization suites to be carried out without real time input or requiring engineering interaction o Module level test program ownership for overall SOC products for all IP items; including but not limited to parametric tests, analog and digital PLLs, SCAN, ATPG, LBIST, SRAM, eDRAM and functional exercisers (AVPs) o Developed parallel test methodology for IBM Multi Chip Modules to allow parallel testing of up to 6 die per module resulting in massive throughput improvements and test cost savings o Responsible for multiple test method developments for real time test pattern modification to enable per chip solutions. These solutions were required for testing of array repair, array analog voltage and sense timings, temperature sensors and functional exercisers
o Lead a team of individuals during development, implementation, testing, manufacturing, qualification and customer support of semiconductor memories o Supported quality topics, internal and external qualifications and ISO requirements, reliability coverage, customer returns and manufacturing capacities and yield o Supported customer design in activities for the device including on site support and intense cooperation with customers and systems/application engineering
o Managed Known Good Die (KGD) qualifications both internally and at customer o Highlighted yield improvements, test time reductions and new design for test features o Managed and oversaw handling of customer returns and closure in shortest amount of time possible o Provided support to other teams new to the KGD arena providing high level of support and understanding
o Defined, documented and implemented wafer level burn-in for multiple KGD products o Ensured die level quality equal to server grade component level including many improvements and design for test features o Maintained position as lead technical contact for wafer level burn-in within the company
o Logic applications/equipment engineer on Teradyne J9xx, Advantest 66xx and 67xx, Micro Control Company burn-in with test systems. o Worked to deliver over $300million in equipment/hardware as well as cost savings of $1million to $4million a year, each year. o Test applications engineering including test program improvement and time reduction as well as tester calibration routine modification to meet stringent customer demands.