Shenzhen, Guangdong, China
Postion: Camera Engineer Duties: As a camera engineer, I develop hardware and software for industrial camera with USB3.0 bus, such as UVC, U3V standard; GigE vision technical camera with single-core DSP; multi-core DSP intelligent camera with 100M/1000M ethernet interface. (1) 17/05 – 18/02 USB3.0 industrial camera develop,such as UVC,SDK; (2) 18/03 – 18/11 GigE industrial camera develop; (3) 18/12 – 19/07 Intelligent industrial camera develop; (4) 19/09 – 20/06 Intelligent industrial camera develop with multi-core SOC (5) 20/07 – 20/09 Camera design for USB3 vision with USB3014 (6) 20/09 – 21/04 U3V camera design on FPGA (7) 21/05 – Present Machine vision on NI VISION
Postion: Software Engineer, customer enabling team Duties: as a software engineer of QAT customer enabling team, I engaged in QAT new feature develop and testing. (1) 16/05 – 16/12 QAT new feature develop and testing After joining QAT, I am responsible for testing of new feature on simics, and QAT driver improvement for linux virtual machines.
Postion: Software Engineer, WCDMA team, HNS Duties: as a software engineer of WCDMA team, I engaged in WCDMA uplink develop, including analyse tool, system test, DFE develop on CEVA, and TIP testing on simics. (1) 14/05 –15/03 WCDMA analyse tool develop In order to probe the PPL status in running, a tool is necessary to dump status messages from CEVA to ARM within 100 cycles. After using efficiently CEVA instructions and internal bus width, I provided some interfaces on CEVA with little influence on PPL, and collected all messages on ARM of T3K chip. With help of DbgApi of CEVA IDE, I analyzed and profiled the ceva executable to get all kinds of useful data structures. I used this information and dumped messages as input to display PPL status in graphic mode. (2) 15/04 –15/11 Implementation of DFE on CEVA DFE( digital front end) is a project from other department, including DDC, DUC, such as Filter, CFR, NCO and LBT. I was responsible for NCO and LBT. I integrated corrdic into LUT to use VCU of CEVA efficiently, and average 0.14 cycles cost in doing NCO for a sample. LBT is used to calculate power spectrum, I changed algorithm to use CEVA VCU to do FFT and power spectrum efficiently. (3) 15/12 –16/04 simulation of TIP on simics In order for TIP develop, I was asked to setup a testing environment for Deverton on simics. I ran a virtual linux for deverton on simics, and had network ready from linux virtual machine to physical network. Then I integrated part of testsuite tool onto linux simultor, got data from TIP simulator module on simics, and collected messages from testsuite PC terminal.
Postion: Software Engineer, wireless DSP team Duties: as a software engineer member of wireless DSP team, I took part in WCDMA uplink develop, including C++ module, PPL UL softwre, driver and system test. (1) 11/04 – 11/07 Performance evalution on XC323 and 3G UE (2) 11/08 – 11/11 develop of 3G C++ simulator for NodeB and UE I spent 3 months in San Diego in develop C++ simulators for wcdma uplink receiver of NodeB, and uplink transmitter of UE. I was responsible for dch rate matching parameter calculation, finger search algorithm of rake receiver, and signature detection. (3) 11/11 – 12/01 integration of asic C++ modules into FXP NodeB Some WCDMA hardware modules were used in mspd wireless SOC, including RPD, PSC, COR-C , CPR-T and FEC. In order to simulate hardwar modules, I modified achitecture of FXP simultor for NodeB to integrate these hardware C++ simulators, and kept their output same between FXP simultor and hardware simulator. I became familiar with the structure and usage of these hardware modules. (4) 12/02 – 12/07 Support to PPL UL develop with C++ modules I improved hardware C++ modules and completed driver for PPL UL with these C++ simultors, then PPL ul was able to run without SOC. It reduced PPL UL debug complexity. (5) 12/08 – 12/09 develop testMac for PCL on T3K (6) 12/10 – 12/12 develop of PPL UL using hardware c++ simulator, I maintained virtual driver of PPL. Then I took part in ppl ul develop, including RM paremeter calculation, decoding of rach, dch and edch. (7) 12/12 – 13/03 debug of PPL UL and testMac With vc2010, I had test on PPL UL with support of simuator and fixed its logic error preliminarily. some issues were removed until it was able to process some of dch testvectors correctly. (8) 13/04 – 14/05 test of PPL UL I was responsible for ppl ul fec unit test,then system test. I maintained UE simulator and generated test-vectors with it for PPL on NodeB. dch coverage test was completed.
Postion: Software Engineer, DSP team Duties: As a software engineer in DSP team of Mindspeed, I engaged in voice and video codec R&D on DSP, including chip of Mindspeed and CEVA, a kind of DSP of CEVA company. I had experience of video and voice, including H.263,H.264, G.723.1, G.729, GSM HR. (1) 09/2-09/4 GSM HR codec optimization on MATTISE After boarding on Mindspeed, I took charge of GSM HR codec optimization on Mattise, the DSP of Mindspeed．its density must be improved by more than 30% . I re-wrote most of assembly routines with c64 assembly in mixed-mode, and improved its density by about 23%. (2) 09/5-09/10 H.263 codec develop & optimization on MATTISE I wrote a H.263 baseline trancoder, including decoder and encoder for Mattise, then, I improved the codec with c64 assembly. a single core had ability to do 15 fps transcoding from CIF into QCIF resolution. (3) 09/10-09/12 G.723.1 codec optimization on CEVA Ａll voice codecs were ported onto ceva, furthmore, to be optimized. I was in charge of G.723.1 codec of mindspeed. After more than two months of optimizing experience, its performance was reduced down to 7mips, and I became familiar with CEVA and G.723.1 standard and algorithm. (4) 09/12-10/11 H.264 codec develop and optimization on CEVA As T4K, an new generation of SOC of Mindspeed, was dsigned for wireless, a series of video codecs had to be ported onto CEVA, such as H.263,H.264, MP4 and JPEG. I was in charge of H.264 decoder and JPEG decoder. I gave tcb interface to H.264 decoder and JPEG decoder. After optimizing, single CEVA had ability to decode h.264 streams about 150fps with resolution of CIF. (5) 10/12-11/04 GSM HR codec optimization on CEVA The CODECs of GSM HR and G.729E were ported on CEVA with special TCB interface, then GSM HR was optimized up to18mips for encoder and 3 mips for decoder.
Postion: Software Engineer, digital media Duties: Ａs softerware engineer, I was responsible for H.264 encoder on Hi3510 and Hi3511, the media processors of Hisilicon. In details, I had experience in rate-control, H.264 encoder on Hi3510, Deinterlace, MPEG4 decoder on ARM926, and H.264 encoder on Hi3511. (1) 05/09-06/01 Bitrate-control on Hi3510 After I was employed by hisilicon, I was asked to improve rate-control algorithm on Hi3510, the TR4 vision media processor of hisilicon. The algorithm was improved to control bitrate accurately, and I was familiar with Hi3510 processor. (2) 06/02-06/10 H.264 encoder on Hi3510 After rate-control improvement, I took charge of H.264 encoder for chip verification, I completed H.264 encoder for Hi3510 testing. Afterwards, I took part in develop of Hi3510 encoder and was responsible for Hi3510 H.264 encoder until October. (3) 06/10-06/12 MPEG4 decoder on Hi3510 After Hi3510 passed TR5 and was brought to market rapidly, I was responsible for MPEG4 decoder on ARM of Hi3510, the decoder had to decode MPEG4 SP bitstream with 512kbps rate and CIF size in realtime through optimization. After VLC tables were reduced, encoder on ARM was able to run in enough efficiency. (4) 06/12-07/03 Deinterlace algorithm on Hi3510 After MPEG4 decoder’s optimization, I was asked to evaluate feasibility of deinterlace algorithm on Hi3510. Since software ran on ARM not quickly enough, advanced deinterlace algorithm was researched to provide support to Hi3511, which was being designed. (5) 07/03-08/05 H.264 encoder on Hi3511 I devoted myself to develop H.264 encoder in the rest time of my staying in Hisilicon. In the former period, I researched encoder algorithm, and gave design of H.264 encoder, In the following months, I wrote H.264 encoder firmware for Hi3511 SOC.
Postion: Hardware Engineer, media hardware department Duties: as hardware engineer, I was responsible for maintenance and develop of IPU/IPCAMERA/TERMINAL/STB boards. In ZTE, I specialized in BF533, the BlackFin media processor of ADI. (1) 03/04-03/05 Trial period, maintainence boards The period of first 3 months was my informal employment, and I was in charg of maintenance of IPU board and V.35 board.It took my great efforts to understand its complex logic in style of schematic in the FPGA; I followed a experienced engineer to complete it. (2) 03/05-03/10 Develop low-cost video conference terminal. As for video conference system of MultiMedia product line of ZTE, a kind of low-cost design was developped to meet market equirement with an achitecture of “MIPS + DM642”. I was responsible for hardware, designed schematic, instructed EDA to layout PCB, debuged the boards, completed reliability experiments on the boards. With help of DDK, drivers were written to test DM642 parts on the boards, software on Linux were provided by software engineers to test sub-sytem of AU1300. (3) 03/10-04/01 Develop IPCAMERA on BF533. A project of IPCAM on BF533 about MPEG4 was put into practice, I was responsible for hardware. When the schemetic and PCB were ready, project was aborted. (4) 04/02-04/12 Develop STB on BF533. ADI new solution of “FUSIV + BLACFIN” was adopted as solution to IPTV by Multimedia department of ZTE, and I was in charge of hardware for STB. I completed design of schemetic and PCB, fixed issues of the boards, and provided boards for software group members. Rreliability experiments on the boards were completed; I was in charge of hardware in the project until I left ZTE.