Orlando, Florida, United States
Domains: Computer Architecture || MIPS || RISCV || x86 || Digital Design || RTL Design || Verification || UVM || DFT || Physical Design Currently an Engineer at AMD. GPU guy. During my first semester I got the insight and understanding of single core architecture, basics of Design Principles. I got an opportunity to work under Professor Eric Rotenberg in my 1st year of my masters. My aim of the project was to develop History Based High Reliable Hybrid Value Predictors where I got the opportunity to work with 721 simulator. In this simulator, we were given access to 9 Pipeline stages, namely: Fetch, Decode, Rename, Renamer, Register Read, Execute, Issue Queue, Write back and Retire. The sole reason was using these Value Predictors was to break the True Dependence (Read After Write) between Instructions speculatively to exploit Instruction Level Parallelism. I had experimented this on various benchmark traces like Bzip, Hmmer and Astar. Knowledge on : Design Verification: Object Oriented Programming Concepts like Inheritance, Static Variables and Classes, Polymorphism (Child and Parent Assignments, Virtual Methods, Abstract Classes), System Verilog Assertions (Concurrent and Temporal), Constraints and Coverage Closure (Code Coverage Vs Functional Coverage), System Verilog, Verilog RTL Design : Static Timing Analysis, Asynchronous Resets Vs Synchronous Resets, Verilog, Clock Domain Crossings (Asynchronous FIFO & Resynchroniser), Finite State Machines, Flip Flops Vs Latches Computer Architecture : Cache Parameters (for Design) and its Performance Analysis (block size, associativity and capacity), Multi-core Architecture, Amdahl’s Law; Cache Coherence, Cache Coherence Protocols (MSI, MESI and MOESI), some exposure for the following areas: (1) Coherence Vs Consistency (2) Virtual Memory Pipeline basics, RISCV (5 stage pipeline knowledge), Issues in Pipeline (more deeper or not?), Structural Hazard, Control Hazard, Data Hazard (RAW, WAR, WAW), Superscalar Processors, Out of Order Execution Speculative Execution – Branch Prediction (accuracy and penalty cost), Reducing Miss Penalty, Branch Target Buffer, Static Vs Dynamic Branch Prediction, Bimodal, G_Share and Hybrid & Performance Analysis Advanced Microarchitecture Knowledge (High Level Overview): Run-ahead Execution, Multi-path Execution, Value Prediction, Simultaneous Multithreading, Memory Disambiguation, Load Store Dependence, Interrupts Vs Exceptions Handling in Tomasulo’s Algorithm Email: [email protected]
*Design Verification for Geometry Enginer GC (Top) Level Team** ********************************************************************
*Extended Support to Geometry Engine Block Team* - Extended support to Block Team was smooth bring up and easy co-ordination with the Top (GC) team. - I was responsible own 5 features. My contribution involved test plan implementation after reading the specs, testbench updates, communication with designers/architects/ - I added a few assertions and wrote directed tests for feature bring-up and made sure they were smoothly enabled without any delays. Enabled the features with macro supports. - Further, I coordinated with GC level (Top Level Subsystem) to make sure the registers were mapped correctly for the new process before they could start with the verification. The registers were tested from the block level and from the top level to eliminate the chances of register address mismatch issues/memory allocation or usage of eliminated registers. -I triaged and debugged few issues related to test hanging issues, c-model failures, and test library issues as well. In this process, I discovered 2 bugs related to Block which had the potential effect of giving incorrect coverage results and timely informed the architects about it.
*Responsible for Geometry Subsystem at GC (Top) Level* -Triaged Issues related to C-model failures, hang, credit-debit mismatch issues. - Responsible for Regression Momentum. Triaged, launched, and tweaked certain arguments based on the Design and Verification Leads requirements. - Extended Support to Team Members on various issues related to Shader, Command Processor and Primitive Assembler Blocks. Miscellaneous Work: - I worked with the Program Management Team and made sure to provide timely updates for JIRA which were deferred from previous projects to current projects. I further cloned the JIRAs and highlighted them with correct tags, fields and descritpion.
- Responsible for running scripts on UXM Machine for emulation purposes. - Co-ordinated with the software team to validate the runs and debugged specific registers as and when needed. - Verified crc32 logic in the upcoming project for the WiFi protocols.
- Responsible for Data Collection for Transportation Student for Analysis of Seatbelt Safety. - Used ArcGIS tool to find the minimum routing distance of the Bridges. - Based on Thermal and Heat Signatures , calculated the most shortest path and which Bridges could be eliminated. - Made use of Raster tool and Mosaic tool to identify weighs and costs respectively.
- Worked on CPU project to implement History-Based Hybrid Value Predictors under the guidance of Professor Eric Rotenberg. Were given access to Trace Processor and had to work on Real Processor. - Analyzed the performances for various types of predictor models like last value predictor, stride value predictor and multiple context based predictor. The main purpose of these value predictors was to speculatively break the true data dependence in Super Scalar Processors. - Various recovery mechanism were observed for recovery like backward walk for active list in case of misprediction. The confidence bit is the determining factor to make a prediction for specific instruction. Languages Used: C++ Challenges Faced: Identifying the threshold value for the confidence bit to make prediction, Backward Walk Active List, Identifying the initial Step (Perfect Value Predication).
- Delivered Fries and Burgers To the Customers. - Kept track of dine in and takeout orders. - Effecient Time Management and responsible enough for delivering food. - Served Burgers, Fries, Tots, Tenders , Juices etc