Greater Dresden Area
• IC package co-design to ensure a seamless integration of the IC in State-of-the-Art packages • consider package design topics right from the initial stages of chip development. • Experience in all phases of electronic hardware development with special focus on fine pitch substrates for IC packages. • Design, layout and optimization of flip-chip packages and System-In-Package. • Power integrity and signal integrity (co-)simulation, including 3D-em-simulation of the package. • Coordination of prototype production. • Initial operation of hardware prototypes and creation of reference designs. EDA tools: Cadence Allegro, Mentor Xpedetion, Zuken CR-8000, CST Studio Suite, SiWave, Altium Designer, ADS, HSpice, Python, Matlab
• IC package co-design to ensure a seamless integration of the IC in State-of-the-Art packages • consider package design topics right from the initial stages of chip development. • Design, layout and optimization of flip-chip packages and System-In-Package. • Power integrity and signal integrity (co-)simulation, including 3D-em-simulation of the package. • Coordination of prototype production.
Research on advanced IC packaging technologies. • Design and layout of System-In-Packages and Submodules w/ high-IO-count-flip-chip-ICs, multiple low-power memories and PMICs. • Design, layout and initial operation of a circuit board w/ multiple very high speed ADCs/DACs & FPGA w/ high speed Serdes. VHDL design for FPGA driving the ADCs/DACs. • Design, layout and initial operation of a circuit board w/ 60 GHz transmitter/receiver ICs. • VHDL design for 28nm IC (digital-part) including multiple high speed Serdes IPs. • Research on high speed silicon interposer interconnections for HBM and chip-to-chip interconnections. • Development of ADK (Assembly-Design-Kit) to enable an efficient design flow for advanced IC packages.
Development of hard- & sofware components for a novel holographic display prototype. • VHDL design to further improve the algorithms of the holographic display • design and initial operation of circuit boards to test new subcomponents
Development of VerliogAMS parser in Java/AntLR.
Reserch on automatic translation of simulation results into a failure test programm for integrated circuits.