Michael Büchler

Firmware Engineer at DESY

Hamburg, Germany

About

Experience

  • Firmware Engineer at DESY
    Sep 2019 - Feb 2025 · 5 yrs 6 mos

    I was working on all layers of MicroTCA.4-based systems: bringup and debugging of custom hardware (FPGA and/or ADC boards), developing VHDL, help establishing new build flows for Zynq SoCs, and some work on the low-level software (within the Linux OS). The main focus was on VHDL "gateware" development for sure. - Implementation of FPGA interfaces for ADCs/DACs and Gigabit transceiver based links between FPGAs - Implementation of high-speed DSP algorithms in VHDL - Verification of VHDL implementations, mostly using ModelSim and Python for co-simulation - bringup of fast feedback links for the accelerator beam controls - firmware support for a newly developed phasemeter EGSE, developed at the University of Hamburg for the LISA project

  • Student Intern at Fraunhofer IIS
    Mar 2018 - Jun 2018 · 4 mos

    Preparation for my master thesis, working with the existing VHDL codebase of a DVB-S2X (satellite) demodulator.

  • Student Intern at Raytheon Anschütz GmbH Navigationssysteme
    Oct 2015 - Dec 2015 · 3 mos

    Investigation of filter algorithms for radar tracking. It was short (12 weeks) gave me a valuable insight into working with algorithms within MATLAB.

  • Student Intern at J.J. Sietas KG Schiffswerft GmbH & Co.
    Mar 2011 - May 2011 · 3 mos

    Internship as a preparation for studying mechanical engineering (which I did not go on to study). It taught me the use of some basic tools and how to behave in a workshop, but I also got a glimpse of how some of the departments of that shipyard operate (construction, manufacturing).