Fayetteville, Arkansas, United States
Here, I would like to share some of my research experiences from my present job: Device processing & fabrication at nano-scale Photolithography & Exposure • Experience of using various types of photoresist, component of photoresist, ways of photoresist coating, spin coater, different types of backing, dicing saw, thickness measurement • KARL Suss MJB-3 Mask aligner for fabricating different sized devices Metallization, Lift-off & Rapid thermal annealing experience • Process development of metal (Ni) contacts by physical vapor deposition (PVD) • Performed lift-off process for various types of photoresists • Use rapid thermal annealing (RTA) for Ohmic contact Experience of Dry Etch (ICP-RIE), Wet Etch (BOE) & PECVD • Inductive coupled plasma/ ICP-RIE based dry etch • Buffer-oxide (BOE) based wet etching • Plasma enhanced chemical vapor deposition (PECVD) for SiO2 deposition Material, surface & electrical characterization • High-resolution XRD & powder diffraction used for materials (SiC & AlN) characterization: Rocking curve (RC) for peaks position & crystal quality, symmetric & asymmetric scan for screw and mixed/edge dislocation density • Atomic force microscopy (AFM) (D3000 Nanoscope III system for surface roughness • Surface thickness, density & roughness are measured by X-ray reflectance (XRR) • I-V & C-V characterized by HP & Keithley semiconductor/component test system, hot chuck up to 600℃, frequency dependency characterization from 50 Hz to 1 MHz Defect state analysis • Wire bonder to attach wire to the device with the chip carrier • Deep-level transient spectroscopy (DLTS) to identifies charge carrier traps. Clean room experience • Limited clean room experience for ISO class 6 clean room/class 1000 cleanroom. Packaging plan • Low temperature co-fired ceramic (LTCC) substrate/case to use for standalone packaged capacitor device for high temperature testing • Integrate packaged or bare die/unpackaged capacitor using wire bonds to the SiC power module Statistical analysis: Excel, JMP & SAS (DoE-Design of Experiment) • Types of variables, descriptive statistics, confidence interval, hypothesis testing (t/z test) for one/two sample means • Analysis of variance (ANOVA), Simple linear regression, model building & correlation
- Hands-on operation of semiconductor fabrication equipment to develop sophisticated wafer-level processes. Performed device characterization and data collection from RF test equipment and via various metrology tools. Experience of process troubleshooting and recipe optimization from experimental design and execution of a fab engineering trial. - Handled multiple projects in areas involving PVD, thin film depositing, plasma etching/dry etching, wet etching, photolithography, wafer dicing. Knowledge of semiconductor devices and their characterization including standard processing techniques. - Having exposure of GaN based wafer processing. Experience with electrical measurement characterization of semiconductor devices from cryogenic to extreme high temperature. - Experience in statistical coursework of Design of Experiment (DOE) with data analysis using software such as Excel, JMP and SAS. - Semiconductor device packaging based on low temperature co-fired (LTCC) ceramic packaging technology. - Performance of defect states analysis by deep-level transient spectroscopy (DLTS). -Knowledge of AFM for surface morphology and XRD for crystal quality.
Internship Experience Worked on Construction Analysis for CMOS devices (28 nm Node) where I have investigated the transistor architecture process flows by monitoring important features to meet the design requirements which are required for the configuration and qualification completion thorough documentation of results and clearly present and discuss them with other team members in engineering and management forums. Developed a comprehensive understanding about process-integrated semiconductor manufacturing by delving into the critical performance and reliability targets in nanometer-scale devices of both FEOL & BEOL process flows by analyzing cross-sectional TEM characterization technique. Scrutinized internal structure in-depth to understanding of product quality and electrical behavior that will directly contribute product performance, reliability & yield improvement. Familiarized with Unix/K2 Viewer for mask/chip/design layout & Quartz measurement tool. As a team player collaborated effectively with all the loop owners for both FEOL & BEOL shows capable of building strong partnerships with diverse engineers shows the ability to be self-motivated, intellectually curious, and able to work independently with a strong attention to detail. Cultivated myself as a well-organized multitasker, skilled at balancing day-to-day process flow needs with a vision of longer-term development work demonstrated capable of learning fast and adapting to the changing needs of a fast-paced development program.