United States
Experienced in semiconductor mask and layout design, with a strong focus on DFM, photolithography, and advanced process integration. Driven by precision, innovation, and collaboration in chip design and manufacturing
Lead mask design for NVIDIA’s next generation GPUs and AI chips, focusing on design-to-silicon accuracy and manufacturing excellence. Drive process improvements, cross-team collaboration, and automation initiatives to boost efficiency and yield. Mentor engineers and help shape best practices in mask design and verification
Designed and optimized physical layouts for custom SoC and accelerator projects within Oracle hardware business units. Delivered full-custom layout for high-performance digital and analog IPs, working closely with circuit designers on timing, power, and reliability. Executed DRC, LVS, EM/IR, and physical verification using Calibre and Virtuoso. Built layout reuse libraries and introduced automation scripts to streamline floorplan, routing, and verification workflows. Partnered with architecture and CAD teams to resolve process-related issues and improve design convergence