Germany
Development of a low-power Deep Neural Network accelerator on an FPGA -application space: Wireless Communications -architecture design (algorithm, AXI stream interfacing) -RTL design using SystemVerilog -functional verification using SystemVerilog -post-implementation testing and debugging Profiling of GNU Radio-based OFDM Testbed -searching for flowgraph bottlenecks -profiling of multi-threaded C++ code -developing custom GNU Radio blocks to automate profiling
FPGA IP design: -Independently designed, verified and tested FPGA accelerator for high-throughput measurement data processing -Developed multi-threaded C++ for the host CPU -SystemVerilog for design and verification -PCIe, AXI stream, AXI interfacing -Xilinx Zynq Ultrascale+ architecture
Low-power front-end ASIC development: -RTL design in VHDL -functional verification in SystemVerilog (UVM) -functional & code coverage -writing of embedded C code for verification purposes -development of a RISC-V CPU extension, defended as bachelor thesis