Marko Nikolin

Design Verification Engineer at Vtool - Smart Verification

Serbia

About

- Verification of digital systems - Design of digital circuits - System verification - Virtual prototyping and system modeling - Hardware description languages: Verilog, SystemC - Verification languages: System Verilog, UVM - Other languages: C, C++, C#, Java, Python - Revision Control Software: GIT, SVN - Tools used: Mentor Graphics Questa, Cadence NCSim, Altium Designer, Microsoft Visual Studio for C/C#, SAP, Eclipse

Experience

  • Design Verification Engineer at Vtool - Smart Verification
    Sep 2024 - Present · 1 yr 10 mos

  • Design Verification Engineer at Veriest
    Feb 2021 - Sep 2024 · 3 yrs 8 mos

  • Digital Verification Engineer at ELSYS Eastern Europe
    Sep 2017 - Feb 2021 · 3 yrs 6 mos

  • Digital Design and Functional Verification Engineer at Frobas d.o.o.
    Jun 2015 - Sep 2017 · 2 yrs 4 mos

    - Design and Verification consultantcy service to global semiconductor companies. - Virtual prototyping and system modelling in SystemC - Functional verification using SystemVerilog and UVM - Unit testing - Scripting

  • SAP MM and SD Consultant at MK IT Business Solutions
    Oct 2014 - May 2015 · 8 mos

    Consultantcy services to SAP users in MK Group