Lawrenceville, Georgia, United States
Lead Engineer specializing in communications and implementing high-speed algorithms in ASICs and FPGAs. Strong track record designing video/audio data paths and high-speed peripheral interfaces as well as DSP intensive applications. Have worked on the PHY layer of every cable TV digital communication standard for both cable modem/set-top and CMTS. Recently completed the successful implementation and system level test of a clean sheet design DOCSIS 3.1 OFDMA transmitter system. Core Competencies: • ASIC and FPGA Design & Verification and toolsets - Verilog, System Verilog, VHDL, NCSIM, VCS • ASIC and FPGA Synthesis and Timing - Synopsys DC, PrimeTime, Spyglass, Synplify, Quartus, Vivado and ISE. • Expertise in various Cable, Storage, and Interconnect Standards – DAVIC, DOCSIS1.0 through 3.1, SATA, USB, TCP/IP • Architecting Hardware and Software solutions • High Speed Analog and Mixed Signal • Embedded Hardware Design and Embedded Software Programming • Experienced in Requirements Analysis, Specification, Design, Development, Testing/Validation, and Release/Maintenance phases • System Design and Analysis • Digital Signal Processing and Digital Communication Design
Designer for next generation Software Designed Radio (SDR) products.
ASIC Design; DSP for Communications; DOCSIS 3/3.1 design of upstream channel. Architect and lead engineer for a clean sheet design working from the Cable Labs draft specification through block level to working OFDMA transmitter.
ASIC/IP Design, Verification and Test. Clean sheet specification development all the way to IC test. Designs included SATA 2 host, USB host/slave and other high speed interfaces.