France
deep learning / machine learning FPGA
Manage the engineering teams of the French office - recruiting - overseeing administrative activities of the office - interacting with other offices and R&D director of the group In charge of the integration of our video decoder IP in the various SoC of the group. Oversee and architect many parts of the Set-top Box HW developments
Technical lead role in verification and methodology in the group: - create and train a verification team in the French office supporting video decoder verifications and emulations. - lead verification efforts for the designs of our DDR controller, new interconnect and new SoC architecture. - improve design methodology and project hierarchy for multiple projects simultaneously.