Marcus Unertl

About

- >20 years experience in CMOS IC mixed signal & analog layout - Expertise in volatile & non-volatile memory array architectures with high dense on pitch core circuits - Familiar with planar technologies down to 28nm and FinFET technolgies down to 10nm - Expertise on Full Chip verification and tape out procedures including basic DRC/LVS & special verification for IP & Chip finishing for FabIn - Expertise in usage of RET methodologies - Expertise on Cadence Virtuoso incl. VXL, Assura & Mentor Calibre - Familiar in intergration & interaction of FullCustom layout flow w/ Synopsys & Cadence based SemiCustom layout flow - delegation at P.R.China in 2008 - strong social and intercultural competencies

Experience

• Senior Staff Specialist Non-Volatile Memory Design at Infineon Technologies
  Aug 2023 - Present · 2 yrs 11 mos

  Full Custom analog physical design for Non Volatile Memory solutions in high end technologies

• N/A (non disclosure) at DR. JOHANNES HEIDENHAIN GmbH
  Nov 2017 - Aug 2023 · 5 yrs 10 mos

  Full Custom analog & Digital (P&R) layout and verification for inhouse ASIC devices Support and execution from 'scratch' until FabIn delivery

• IC layout engineer at INTEL Deutschland GmbH
  Aug 2012 - Oct 2017 · 5 yrs 3 mos

  Analog IC layout engineer Layout for PHY modules - e.g. MPHY - at high end planar & FinFET technologies

• IC layout engineer DRAM development at ELPIDA MEMORY (Europe) GmbH
  Jun 2009 - Jul 2012 · 3 yrs 2 mos

  Realisation and verification of analog & digital Full Custom IC layout for DRAM products in high end graphic applications (GDDR3 & GDDR5). Link function between FullCustom layout & Synopsys based SemiCustom work flow

• Staff engineer IC layout - Analog & Mixed signal at QIMONDA AG
  Apr 2006 - Jun 2009 · 3 yrs 3 mos

  - Realisation & verification of DRAM memory array layout (512Mb, 1Gb, 2Gb) for technology nodes: 90nm, 80nm, 70nm, 65nm, 46nm - Expertise in trench DRAM memory array layout (90nm-70nm) - Familiar with stacked DRAM memory array in buried wordline architecture (65nm-46nm) - Expertise in usage of RET methodologies (OPC, layout litho simulation) - Expertise in high dense 'on pitch' analog core layout (e.g. Sense Amplifier) - Training & knowledge transfer for team members - Layout team coordination - Continous improvement of layout verification methodology & strategy in cooperation with CAD/PDK department; evaluation & feasibility investigations for DRC design rule improvements in cooperation with technology experts - 06/08 - 12/08: Delegation at Suzhou & Xi'an (PRChina); team coordination, verfication & tape out of final QIMONDA DRAM product in DDR2 application & 65nm buried wordline technology