Barcelona, Catalonia, Spain
20y+ experience in complex electronics design
15+ Hi-speed PCB design
7 FPGA design Altera (RTL-VHDL)
#System Architect#: Open Compute Project OCP, ORv3, AI-HPC server (Intel Xeon and RISC-V SuperChip), Hi-speed Xconnect (Infiniband, UALink, UEC, AFL) from Broadcom and Astera Labs then Silicon Interposer SIP packaging 1kWATT TDP
#Principal Engineer# on hi-speed PCB design: from Design Entry, schema debug scripts, Power Distribution Network design, Constraint Manager Setup, PowerIntegrity (PI) study, Signal Integrity (SI) study, PnR followup, till bring-up and stress-test and Mass Production followup
#RD Director#: can manage up to 5+ different projects in parallel and remotely; broad experience to lead RD off-shore engineering-teams (India and Taiwan)
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CAD: Cadence ALLEGRO-Capture-OrCAD
As AI Server Architect I lead internal teams to develop complex OCP AI solutions that meet our customers' requirements and comply with Open Compute Project ORv3 spec As part of the AVZ project, I cooperate with many stakeholders contributing to Semidynamics XPU development such as chip architects, ASIC Backend team, Silicon Interposer packaging team, PCB team, mechanical team, BMC team and drive discussions with several partners to qualify their silicon technologies for advanced AI solutions In addition to this, I integrate complex scale up and scale out network technologies at Rack / Cluster level such as UALink, AFL, Infiniband, Ethernet, UEC, including switching and network topologies
PCB design consultant for several customers ReticulateMicro (Florida -US), in charge of VAST1 project targeting a portable SDI – HMDI Video capture based on Lantronix SOM; support for Linux UBUNTU BSP integration (MIPI CSI driver on CAMSS Techpack) from BSP team in Hyderabad / India in coop with ZETTAone Bangalore: in charge of ThunderBERRY5 SBC based on Thundercomm SOM C610 Intel AlderLake CPU SBC – technical study Duties included: Product Architecture, BOM definition, Schematic redaction, DesRulesCheck, definition of all Layout DesignRules, Breakout Specs, Place-n-Route follow-up, Manufacturing and bring-up, FCC/EC certify followup Chipset: Qualcomm QRB5165 and Qualcomm QCS610, SEMTEC GS12170, Lontium LT6911, Lontium LT8711 Design: PCie gen2; HDMI1.4; USB3.1; MIPI CSI; MIPI DSI, PMIC CAD: Altium / CADENCE Allegro-OrCAD
In charge of UP-board product architecture (Intel Atom X5) and UP-board roadmap, incluging Altera FPGA fw architecture, RD db revision, product validation and Thermal qualification. The UP-board + RealSense Robotics has been presented at Intel IDF 2016 Shenzhen by Intel VP China
At AAEON Technology Europe (ASUS Associated Company), Duties included: - UP-board product portfolio architecture (8+ products), project management of the RD team in Taiwan: https://up-board.org/ (UP-boards are the most used Intel DEVKIT, sold directly by Intel) - As Intel IOTG Tech Expert: responsible of all AAEON’s Tier1 Accounts in France, Italy and Germany in support of all sales teams of AAEON Europe Chipset: Intel CherryTRAIL, Intel ApolloLAKE, Intel ALTERA Cyclone10GX, Intel Altera MAX10 Design: LPDDR4 mem if; VR13 pwr; PCie gen2; HDMI1.4; USB3.1; MIPI CSI; MIPI DSI CAD: Altium / CADENCE Allegro-OrCAD
Blysco (startup incubated by CEA) aimed to design, industrialize and commercialize a new class of enterprise low power servers based on ARMv8, 64bit processor class Cortex A57. Such project has been supported by CEA-Leti, STMicroelectronics Crolles within the frame of FD-SOI market development. In the position of Director of RD, I assumed the responsibility of several tasks: product definition and specification for both system processor and server embodiment, product roadmap and innovation strategy, market analysis, advanced research projects on HyperShare Xconnect, Si-Photonics, 3D-IC. I represented Blysco for the cooperative project Euroserver/FP7. I lead many technical sessions with experts and managers of ARM, STM, CEA-Leti. I was an invited speaker to some international conferences and workshops such as DATE12 in Dresden for the Panel: "Key Challenges For The Next Generation of Computing Systems Taming the Data Deluge", panel organized by EU Project Officers and Hipeac (Computing System Week, Oct12) in Ghent.